74LVC02APW,112 NXP

74LVC02A Quad 2-input NOR gate Rev. 9 24 August 2020 Product data sheet 1. General description The 74LVC02A provides four 2-input NOR gates. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V applications. 2. Features and benefits 5 V tolerant inputs for interfacing with 5 V logic Wide supply voltage range from 1.2 V to 3.6 V CMOS low power consumption Direct interface with TTL levels Complies with JEDEC standard: JESD8-7A (1.65 V to 1.95 V) JESD8-5A (2.3 V to 2.7 V) JESD8-C/JESD36 (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-B exceeds 200 V CDM JESD22-C101E exceeds 1000 V Specified from -40 C to +85 C and -40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC02AD -40 C to +125 C SO14 plastic small outline package 14 leads SOT108-1 body width 3.9 mm 74LVC02ADB -40 C to +125 C SSOP14 plastic shrink small outline package 14 leads SOT337-1 body width 5.3 mm 74LVC02APW -40 C to +125 C TSSOP14 plastic thin shrink small outline package SOT402-1 14 leads body width 4.4 mm 74LVC02ABQ -40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal SOT762-1 enhanced very thin quad flat package no leads 14 terminals body 2.5 3 0.85 mmNexperia 74LVC02A Quad 2-input NOR gate 4. Functional diagram 2 1 1 3 5 1 4 2 1A 1 6 1Y 3 1B 5 2A 4 2Y 8 6 2B 1 10 9 8 3A 10 3Y 9 3B A 11 11 4A 1 4Y 13 13 Y 12 4B 12 B mna216 mna217 mna215 Fig. 1. Logic symbol Fig. 2. IEC logic symbol Fig. 3. Logic diagram (one gate) 5. Pinning information 5.1. Pinning 74LVC02A terminal 1 index area 1A 2 13 4Y 1B 3 12 4B 2Y 4 11 4A 74LVC02A 5 10 2A (1) 3Y GND 1Y 1 14 V CC 2B 6 9 3B 2 13 1A 4Y 3 12 1B 4B 001aac920 2Y 4 11 4A 5 10 2A 3Y Transparent top view 6 2B 9 3B (1) This is not a ground pin. There is no electrical or GND 7 8 3A mechanical requirement to solder the pad. In case 001aac919 soldered, the solder land should remain floating or connected to GND. Fig. 4. Pin configuration for SOT108-1 (SO14), SOT337-1 (SSOP14) and SOT402-1 (TSSOP14) Fig. 5. Pin configuration for SOT762-1 (DHVQFN14) 5.2. Pin description Table 2. Pin description Symbol Pin Description 1Y to 4Y 1, 4, 10, 13 data output 1A to 4A 2, 5, 8, 11 data input 1B to 4B 3, 6, 9,12 data input GND 7 ground (0 V) V 14 supply voltage CC 74LVC02A All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 9 24 August 2020 2 / 13 GND 7 1 1Y 3A 8 14 V CC