74LVC16374ADL,112 NXP

74LVC16374A 74LVCH16374A 16-bit edge-triggered D-type flip-flop 5 V tolerant 3-state Rev. 12 20 November 2018 Product data sheet 1. General description The 74LVC16374A and 74LVCH16374A are 16-bit edge-triggered flip-flops featuring separate D-type inputs with bus hold (74LVCH16374A only) for each flip-flop and 3-state outputs for bus- oriented applications. It consists of two sections of eight positive edge-triggered flip-flops. A clock input (nCP) and an output enable (nOE) are provided for each octal. The flip-flops store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. When pin nOE is LOW, the contents of the flip-flops are available at the outputs. When pin nOE is HIGH, the outputs go to the high-impedance OFF-state. Operation of input nOE does not affect the state of the flip-flops. Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be applied to the outputs. These features allow the use of these devices in mixed 3.3 V and 5 V applications. Bus hold on data inputs eliminates the need for external pull-up resistors to hold unused inputs. 2. Features and benefits 5 V tolerant inputs/outputs for interfacing with 5 V logic Wide supply voltage range from 1.2 V to 3.6 V CMOS low power consumption Multibyte flow-through standard pinout architecture Low inductance multiple supply pins for minimum noise and ground bounce Direct interface with TTL levels All data inputs have bus hold (74LVCH16374A only) High-impedance outputs when V = 0 V CC Complies with JEDEC standard: JESD8-7A (1.65 V to 1.95 V) JESD8-5A (2.3 V to 2.7 V) JESD8-C/JESD36 (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-B exceeds 200 V CDM JESD22-C101E exceeds 1000 V Specified from -40 C to +85 C and -40 C to +125 CNexperia 74LVC16374A 74LVCH16374A 16-bit edge-triggered D-type flip-flop 5 V tolerant 3-state 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC16374ADL -40 C to +125 C SSOP48 plastic shrink small outline package SOT370-1 48 leads body width 7.5 mm 74LVC16374ADGG -40 C to +125 C TSSOP48 plastic thin shrink small outline package SOT362-1 48 leads body width 6.1 mm 74LVCH16374ADGG 4. Functional diagram 1 EN1 1OE 48 1 24 1CP C3 24 2OE EN2 25 1OE 2OE 2CP C4 47 1D0 1Q0 2 47 2 1D0 3D 1 1Q0 46 1D1 1Q1 3 46 3 1D1 1Q1 44 1D2 1Q2 5 44 5 43 1D3 1Q3 6 1D2 1Q2 43 6 41 1D4 1Q4 8 1D3 1Q3 41 8 40 1D5 1Q5 9 1D4 1Q4 40 9 38 1D6 1Q6 11 1D5 1Q5 38 11 37 1D7 1Q7 12 1D6 1Q6 37 12 36 2D0 2Q0 13 1D7 1Q7 35 2D1 2Q1 14 36 13 2D0 4D 2 2Q0 33 2D2 2Q2 16 35 14 2D1 2Q1 32 2D3 2Q3 17 33 16 2D2 2Q2 30 2D4 2Q4 19 32 17 2D3 2Q3 29 2D5 2Q5 20 30 19 2D4 2Q4 27 2D6 2Q6 22 29 20 2D5 2Q5 26 2D7 2Q7 23 27 22 2D6 2Q6 1CP 2CP 26 23 2D7 2Q7 48 25 001aaa253 001aaa254 Fig. 1. Logic symbol Fig. 2. IEC logic symbol 1D0 D Q 1Q0 2D0 D Q 2Q0 CP CP FF1 FF2 1CP 2CP 1OE 2OE to 7 other channels to 7 other channels 001aaa255 Fig. 3. Logic diagram 74LVC LVCH16374A All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2018. All rights reserved Product data sheet Rev. 12 20 November 2018 2 / 15