74LVC2G34GS NXP

74LVC2G34 Dual buffer gate Rev. 9 15 December 2016 Product data sheet 1. General description The 74LVC2G34 provides two buffers. Inputs can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in a mixed 3.3 V and 5 V environment. This device is fully specified for partial power-down applications using I . OFF The I circuitry disables the output, preventing the damaging backflow current through OFF the device when it is powered down. 2. Features and benefits Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant inputs for interfacing with 5 V logic High noise immunity Complies with JEDEC standard: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8B/JESD36 (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V 24 mA output drive (V =3.0 V) CC CMOS low power consumption Latch-up performance exceeds 250 mA Direct interface with TTL levels Multiple package options Specified from 40 Cto+85 C and 40 C to +125 C.74LVC2G34 Nexperia Dual buffer gate 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC2G34GW 40 Cto +125 C SC-88 plastic surface-mounted package; 6 leads SOT363 74LVC2G34GV 40 Cto +125 C TSOP6 plastic surface-mounted package (TSOP6); 6 leads SOT457 74LVC2G34GM 40 Cto +125 C XSON6 plastic extremely thin small outline package; no leads; SOT886 6 terminals; body 1 1.45 0.5 mm 74LVC2G34GF 40 C to +125 C XSON6 plastic extremely thin small outline package; no leads; SOT891 6 terminals; body 1 1 0.5 mm 74LVC2G34GN 40 C to +125 C XSON6 extremely thin small outline package; no leads; SOT1115 6 terminals; body 0.9 1.0 0.35 mm 74LVC2G34GS 40 C to +125 C XSON6 extremely thin small outline package; no leads; SOT1202 6 terminals; body 1.0 1.0 0.35 mm 74LVC2G34GX 40 C to +125 C X2SON6 plastic thermal extremely thin small outline package; SOT1255 no leads; 6 terminals; body 1 0.8 0.35 mm 4. Marking Table 2. Marking [1] Type number Marking code 74LVC2G34GW YA 74LVC2G34GV Y34 74LVC2G34GM YA 74LVC2G34GF YA 74LVC2G34GN YA 74LVC2G34GS YA 74LVC2G34GX YA [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram  $ <   $ <    $ < PQ QE P DFD Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one gate) 74LVC2G34 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 9 15 December 2016 2 of 18 E