74LVC2G34GW-Q100,1 Nexperia

74LVC2G34-Q100 Dual buffer gate Rev. 4 7 October 2021 Product data sheet 1. General description The 74LVC2G34-Q100 is a dual buffer. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power-down applications using I . The I circuitry OFF OFF disables the output, preventing the damaging backflow current through the device when it is powered down. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 C to +85 C and -40 C to +125 C Wide supply voltage range from 1.65 V to 5.5 V Overvoltage tolerant inputs to 5.5 V High noise immunity Complies with JEDEC standard: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8C (2.7 V to 3.6 V) JESD36 (4.5 V to 5.5 V) ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) 24 mA output drive (V = 3.0 V) CC CMOS low power dissipation I provides partial Power-down mode operation. OFF Latch-up performance exceeds 250 mA Direct interface with TTL levels Multiple package options 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC2G34GW-Q100 -40 C to +125 C SC-88 plastic surface-mounted package 6 leads SOT363 74LVC2G34GV-Q100 -40 C to +125 C SC-74 plastic surface-mounted package 6 leads SOT457 TSOP6 74LVC2G34GM-Q100 -40 C to +125 C XSON6 plastic extremely thin small outline package SOT886 no leads 6 terminals body 1 1.45 0.5 mmNexperia 74LVC2G34-Q100 Dual buffer gate 4. Marking Table 2. Marking Type number Marking code 1 74LVC2G34GW-Q100 YA 74LVC2G34GV-Q100 Y34 74LVC2G34GM-Q100 YA 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram 1 1 1A 1Y 6 1 6 3 2A 2Y 4 1 3 4 A Y mnb063 mnb064 001aac536 Fig. 1. Logic symbol Fig. 2. IEC logic symbol Fig. 3. Logic diagram (one gate) 6. Pinning information 6.1. Pinning 74LVC2G34 74LVC2G34 1A 1 6 1Y 1 6 1A 1Y GND 2 5 V CC 2 5 GND V CC 2A 3 4 2Y 2A 3 4 2Y 001aab677 001aab676 Transparent top view Fig. 4. Pin configuration SOT363 (SC-88) and SOT457 (SC-74 TSOP6) Fig. 5. Pin configuration SOT886 (XSON6) 6.2. Pin description Table 3. Pin description Symbol Pin Description 1A 1 data input GND 2 ground (0 V) 2A 3 data input 2Y 4 data output V 5 supply voltage CC 1Y 6 data output 74LVC2G34 Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 4 7 October 2021 2 / 12