74LVT574PW,112 NXP

74LVT574 74LVTH574 3.3 V octal D-type flip-flop 3-state Rev. 7 22 November 2011 Product data sheet 1. General description The 74LVT574 74LVTH574 is a high-performance product designed for V operation at CC 3.3 V. This device is an 8-bit, edge triggered register coupled to eight 3-state output buffers. The two sections of the device are controlled independently by the clock (pin CP) and output enable (pin OE) control gates. The state of each Dn input (one setup time before the LOW-to-HIGH clock transition) is transferred to the corresponding flip-flops Qn output. The 3-state output buffers are designed to drive heavily loaded 3-state buses, MOS memories, or MOS microprocessors. The active LOW output enable (pin OE) controls all eight 3-state buffers independent of the clock operation. When pin OE is LOW, the stored data appears at the outputs. When pin OE is HIGH, the outputs are in the high-impedance OFF-state, which means they will neither drive nor load the bus. 2. Features and benefits Inputs and outputs arranged for easy interfacing to microprocessors 3-state outputs for bus interfacing Common output enable control TTL input and output switching levels Input and output interface capability to systems at 5 V supply Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs Live insertion and extraction permitted No bus current loading when output is tied to 5 V bus Power-up reset Power-up 3-state Latch-up protection JESD78 class II exceeds 500 mA ESD protection: HBM JESD22-A114E exceeds 2000 V MM JESD22-A115-A exceeds 200 V Specified from 40 C to +85 C74LVT574 74LVTH574 NXP Semiconductors 3.3 V octal D-type flip-flop 3-state 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVT574D 40 C to +85 C SO20 plastic small outline package 20 leads SOT163-1 body width 7.5 mm 74LVTH574D 74LVT574DB 40 C to +85 C SSOP20 plastic shrink small outline package 20 leads SOT339-1 body width 5.3 mm 74LVTH574DB 74LVT574PW 40 C to +85 C TSSOP20 plastic thin shrink small outline package 20 leads SOT360-1 body width 4.4 mm 74LVTH574PW 74LVT574BQ 40 Cto+85 C DHVQFN20 plastic dual in-line compatible thermal enhanced very SOT764-1 thin quad flat package no leads 20 terminals body 2.5 4.5 0.85 mm 4. Functional diagram 1 EN2 11 11 C1 CP 2 19 D0 Q0 2 19 1D 2 3 18 D1 Q1 17 3 18 4 D2 Q2 5 16 4 17 D3 Q3 6 15 5 16 D4 Q4 7 14 D5 Q5 6 15 8 13 D6 Q6 7 14 9 12 D7 Q7 OE 8 13 1 mna798 9 12 001aae466 Fig 1. Logic symbol Fig 2. IEC logic symbol D0 D1 D2 D3 D4 D5 D6 D7 D D D D D D D D CP Q CP Q CP Q CP Q CP Q CP Q CP Q CP Q CP OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 001aae467 Fig 3. Logic diagram 74LVT LVTH574 All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved. Product data sheet Rev. 7 22 November 2011 2 of 17