74LVX574 LOW VOLTAGE CMOS OCTAL D-TYPE FLIP-FLOP (3-STATE NON INV.) WITH 5V TOLERANT INPUTS HIGH SPEED: f = 125MHz (TYP.) at V = 3.3V MAX CC 5V TOLERANT INPUTS POWER-DOWN PROTECTION ON INPUTS INPUT VOLTAGE LEVEL: V = 0.8V, V = 2V at V = 3V IL IH CC SOP TSSOP LOW POWER DISSIPATION: I = 4 A (MAX.) at T =25C CC A LOW NOISE: Table 1: Order Codes V = 0.3V (TYP.) at V =3.3V OLP CC PACKAGE T & R SYMMETRICAL OUTPUT IMPEDANCE: I = I = 4 mA (MIN) at V =3V SOP 74LVX574MTR OH OL CC BALANCED PROPAGATION DELAYS: TSSOP 74LVX574TTR t t PLH PHL OPERATING VOLTAGE RANGE: D inputs. While the (OE) input is low, the 8 outputs V (OPR) = 2V to 3.6V (1.2V Data Retention) CC will be in a normal logic state (high or low logic PIN AND FUNCTION COMPATIBLE WITH level) and while high level the outputs will be in a 74 SERIES 574 high impedance state. The output control does not IMPROVED LATCH-UP IMMUNITY affect the internal operation of flip flops that is, the old data can be retained or the new data can be DESCRIPTION entered even while the outputs are off. The 74LVX574 is a low voltage CMOS OCTAL Power down protection is provided on all inputs D-TYPE FLIP-FLOP with 3 STATE OUTPUT NON and 0 to 7V can be accepted on inputs with no INVERTING fabricated with sub-micron silicon regard to the supply voltage. 2 gate and double-layer metal wiring C MOS This device can be used to interface 5V to 3V. It technology. It is ideal for low power, battery combines high speed performance with the true operated and low noise 3.3V applications. CMOS low power consumption. This 8 bit D-Type flip-flop is controlled by a clock All inputs and outputs are equipped with input (CK) and an output enable input (OE). On protection circuits against static discharge, giving the positive transition of the clock, the Q outputs them 2KV ESD immunity and transient excess will be set to the logic state that were setup at the voltage. Figure 1: Pin Connection And IEC Logic Symbols Rev. 3 August 2004 1/13 Obsolete Product(s) - Obsolete Product(s)74LVX574 Figure 2: Input Equivalent Circuit Table 2: Pin Description PIN N SYMBOL NAME AND FUNCTION 1OE 3-State Output Enable Input (Active LOW) 2, 3, 4, 5, 6, D0 to D7 Data Inputs 7, 8, 9 12, 13, 14, Q0 to Q7 3-State Outputs 15, 16, 17, 18, 19 11 CK Clock Input (LOW-to-HIGH Edge Triggered) 10 GND Ground (0V) 20 V Positive Supply Voltage CC Table 3: Truth Table INPUTS OUTPUT OE CK D Q HX X Z L X NO CHANGE LLL LHH X : Dont Care Z : High Impedance Figure 3: Logic Diagram This logic diagram has not be used to estimate propagation delays 2/13 Obsolete Product(s) - Obsolete Product(s)