74LVX74 LOW VOLTAGE CMOS DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR (5V TOLERANT INPUTS) HIGH SPEED: f = 145MHz (TYP.) at V = 3.3V MAX CC 5V TOLERANT INPUTS INPUT VOLTAGE LEVEL: V =0.8V, V =2V AT V =3V IL IH CC LOW POWER DISSIPATION: SOP TSSOP I = 2 A (MAX.) at T =25C CC A LOW NOISE: Table 1: Order Codes V = 0.3V (TYP.) at V = 3.3V OLP CC SYMMETRICAL OUTPUT IMPEDANCE: PACKAGE T & R I = I = 4mA (MIN) OH OL SOP 74LVX74MTR BALANCED PROPAGATION DELAYS: TSSOP 74LVX74TTR t t PLH PHL OPERATING VOLTAGE RANGE: V (OPR) = 2V to 3.6V (1.2V Data Retention) CC A signal on the D INPUT is transferred to the Q PIN AND FUNCTION COMPATIBLE WITH OUTPUT during the positive going transition of the 74 SERIES 74 clock pulse. CLR and PR are independent of the clock and accomplished by a low setting on the IMPROVED LATCH-UP IMMUNITY appropriate input. POWER DOWN PROTECTION ON INPUTS Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no DESCRIPTION regard to the supply voltage. The 74LVX74 is a low voltage CMOS DUAL This device can be used to interface 5V to 3V D-TYPE FLIP-FLOP WITH PRESET AND CLEAR system. It combines high speed performance with NON INVERTING fabricated with sub-micron the true CMOS low power consumption. All inputs 2 silicon gate and double-layer metal wiring C MOS and outputs are equipped with protection circuits technology. It is ideal for low power, battery against static discharge, giving them 2KV ESD operated and low noise 3.3V applications. immunity and transient excess voltage. Figure 1: Pin Connection And IEC Logic Symbols Rev. 3 August 2004 1/13 Obsolete Product(s) - Obsolete Product(s)74LVX74 Figure 2: Input Equivalent Circuit Table 2: Pin Description PIN N SYMBOL NAME AND FUNCTION Asynchronous Reset - 1, 13 1CLR, 2CLR Direct Input 2, 12 1D, 2D Data Inputs 3, 11 1CK, 2CK Clock Input (LOW to HIGH, Edge Triggered) 4, 10 1PR, 2PR Asynchronous Set - Direct Input 5, 9 1Q, 2Q True Flip-Flop Outputs 6, 8 1Q, 2Q Complement Flip-Flop Outputs 7 GND Ground (0V) 14 V Positive Supply Voltage CC Table 3: Truth Table INPUTS OUTPUTS FUNCTION CLR PR DCK Q Q LH X X L H CLEAR H L X X H L PRESET LL X X H H HH L L H HH H H L Q Q HHX NO CHANGE n n X : Dont Care Figure 3: Logic Diagram This logic diagram has not be used to estimate propagation delays 2/13 Obsolete Product(s) - Obsolete Product(s)