74LVX273 LOW VOLTAGE CMOS OCTAL D-TYPE FLIP-FLOP WITH CLEAR (5V TOLERANT INPUTS) HIGH SPEED: f = 150 MHz (TYP.) at V = 3.3V MAX CC 5V TOLERANT INPUTS POWER-DOWN PROTECTION ON INPUTS INPUT VOLTAGE LEVEL: V = 0.8V, V = 2V at V =3V IL IH CC SOP TSSOP LOW POWER DISSIPATION: I = 4 A (MAX.) at T =25C CC A LOW NOISE: Table 1: Order Codes V = 0.3V (TYP.) at V =3.3V OLP CC PACKAGE T & R SYMMETRICAL OUTPUT IMPEDANCE: I = I = 4 mA (MIN) at V =3V SOP 74LVX273MTR OH OL CC BALANCED PROPAGATION DELAYS: TSSOP 74LVX273TTR t t PLH PHL OPERATING VOLTAGE RANGE: transferred to the Q outputs on the positive going V (OPR) = 2V to 3.6V (1.2V Data Retention) CC edge of the clock pulse. PIN AND FUNCTION COMPATIBLE WITH When the CLEAR input is held low, the Q outputs 74 SERIES 273 are held low independently of the other inputs. IMPROVED LATCH-UP IMMUNITY Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no DESCRIPTION regard to the supply voltage. The 74LVX273 is a low voltage CMOS OCTAL This device can be used to interface 5V to 3V. It D-TYPE FLIP-FLOP WITH CLEAR fabricated with combines high speed performance with the true sub-micron silicon gate and double-layer metal CMOS low power consumption. 2 wiring C MOS technology. It is ideal for low All inputs and outputs are equipped with power, battery operated and low noise 3.3V protection circuits against static discharge, giving applications. them 2KV ESD immunity and transient excess Information signals applied to D inputs are voltage. Figure 1: Pin Connection And IEC Logic Symbols Rev. 3 August 2004 1/12 Obsolete Product(s) - Obsolete Product(s)74LVX273 Figure 2: Input Equivalent Circuit Table 2: Pin Description PIN N SYMBOL NAME AND FUNCTION 1CLEAR Asynchronous Master Reset (Active LOW) 2, 5, 6, 9, 12, Q0 to Q7 Flip-Flop Outputs 15, 16,19 3, 4, 7, 8, 13, D0 to D7 Data Inputs 14, 17, 18 11 CLOCK Clock Input (LOW-to-HIGH Edge Triggered) 10 GND Ground (0V) 20 V Positive Supply Voltage CC Table 3: Truth Table INPUTS OUTPUT FUNCTION DB Q CLEAR L X X L CLEAR HL L HH H Q HX NO CHANGE n X : Dont Care Figure 3: Logic Diagram This logic diagram has not be used to estimate propagation delays 2/12 Obsolete Product(s) - Obsolete Product(s)