CBTW28DD14 14-bit bus switch/multiplexer for DDR2/DDR3/DDR4 applications Rev. 7.1 3 August 2015 Product data sheet 1. General description This 14-bit bus switch/multiplexer (MUX) is designed for 1.5 V or 1.8 V supply voltage operation, POD 12, SSTL 12, SSTL 135, SSTL 15 or SSTL 18 signaling and CMOS select input levels. It is designed for operation in DDR2, DDR3 or DDR4 memory bus systems. The CBTW28DD14 has a 1 : 2 switch or 2 : 1 multiplex topology and offers a 14-bit wide bus. Each 14-bit wide A-port can be switched to one of two ports B and C, for all bits simultaneously. The selection of the port is by a simple CMOS input (SELect). Another CMOS input (ENable) is available to allow all ports to be disconnected. Each port is non-directional due to the use of FET switches, allowing a multitude of applications requiring high-bandwidth switching or multiplexing. The SEL and EN input signals are designed to operate transparently as CMOS input level signals in both 1.5 V and 1.8 V supply voltage conditions. CBTW28DD14 uses NXP proprietary high-speed switch architecture providing high bandwidth, very little insertion loss at low frequency, and very low propagation delay, allowing use in many applications requiring switching or multiplexing of high-speed signals. It is available in a 4.5 mm 4.5 mm TFBGA48 package with 0.5 mm ball pitch, for optimal size versus board layout density considerations. It is characterized for operation from 10 C to +85 C. 2. Features and benefits 2.1 Topology 14-bit bus width 1 : 2 switch/MUX topology Bidirectional operation Simple CMOS select pin (SEL) Simple CMOS enable pin (EN) 2.2 Performance 2.5 GHz bandwidth Low ON insertion loss Low crosstalk High OFF isolation POD 12, SSTL 12, SSTL 135, SSTL 15 or SSTL 18 signalingCBTW28DD14 NXP Semiconductors 14-bit bus switch/multiplexer for DDR2/DDR3/DDR4 applications Low R (10 typical) ON 2.3 General attributes 1.5 V or 1.8 V supply voltage operation Very low supply current (300 A typical) ESD robustness exceeds 3 kV HBM, 1 kV CDM Available in TFBGA48 package, 4.5 mm 4.5 mm 0.8 mm size, 0.5 mm pitch, Pb-free/Dark Green 3. Applications DDR2/DDR3/DDR4 memory bus systems Systems requiring high-speed multiplexing 4. Ordering information Table 1. Ordering information Type number Topside Package marking Name Description Version CBTW28DD14ET W2814 TFBGA48 plastic thin fine-pitch ball grid array package 48 balls SOT1155-1 body 4.5 4.5 0.8 mm CBTW28DD14AET 2814A TFBGA48 plastic thin fine-pitch ball grid array package 48 balls SOT1155-1 body 4.5 4.5 0.8 mm, Cu-OSP leadframe 4.1 Ordering options Table 2. Ordering options Type number Orderable Package Packing method Minimum Temperature part number order quantity CBTW28DD14ET CBTW28DD14ET,118 TFBGA48 Reel 13 Q1/T1 4000 T = 10 Cto+85 C amb *Standard mark SMD CBTW28DD14AET CBTW28DD14AETJ TFBGA48 Reel 13 Q1/T1 4000 T = 10 Cto+85 C amb *Standard mark SMD CBTW28DD14 All information provided in this document is subject to legal disclaimers. NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 7.1 3 August 2015 2 of 14