DSP56303 Freescale Semiconductor Rev. 11, 2/2005 Technical Data DSP56303 24-Bit Digital Signal Processor 16 6 6 3 Memory Expansion Area The DSP56303 is intended for use in telecommunication Triple X Data Y Data PrograM HI08 ESSI SCI Timer RAM RAM RAM applications, such as multi- 2048 24 2048 24 4096 24 line voice/data/ fax bits bits bits (default) (default) (default) processing, video Peripheral conferencing, audio Expansion Area applications, control, and YAB 18 Address External XAB general digital signal Generation Address Unit PAB Bus Address processing. Switch Six-Channel DAB DMA Unit External 24-Bit Bus 13 Interface Bootstrap DSP56300 and Inst. ROM Control Core Cache Control DDB YDB 24 Internal External XDB Whats New Data Bus Data PDB Data Bus Switch Rev. 11 includes the following Switch GDB changes: Adds lead-free packaging and EXTAL Power Management Clock part numbers. Data ALU 5 Generator Program Program Program + 24 24 56 56-bit MAC JTAG XTAL Interrupt Decode Address Two 56-bit Accumulators PLL Controller Controller Generator OnCE 56-bit Barrel Shifter DE 2 MODA/IRQA MODB/IRQB RESET MODC/IRQC PINIT/NMI MODD/IRQD Figure 1. DSP56303 Block Diagram The DSP56303 is a member of the DSP56300 core family of programmable CMOS DSPs. Significant architectural features of the DSP56300 core family include a barrel shifter, 24-bit addressing, instruction cache, and DMA. The DSP56303 offers 100 MMACS using an internal 100 MHz clock at 3.03.6 volts. The DSP56300 core family offers a rich instruction set and low power dissipation, as well as increasing levels of speed and power to enable wireless, telecommunications, and multimedia products. Freescale Semiconductor, Inc., 1996, 2005. All rights reserved. PIO EB PM EB XM EB YM EBTable of Contents Data Sheet Conventions.......................................................................................................................................ii Features...............................................................................................................................................................iii Target Applications .............................................................................................................................................iv Product Documentation ......................................................................................................................................iv Chapter 1 Signals/Connections 1.1 Power ................................................................................................................................................................1-3 1.2 Ground ..............................................................................................................................................................1-3 1.3 Clock.................................................................................................................................................................1-4 1.5 External Memory Expansion Port (Port A) ......................................................................................................1-4 1.6 Interrupt and Mode Control ..............................................................................................................................1-7 1.7 Host Interface (HI08)........................................................................................................................................1-8 1.8 Enhanced Synchronous Serial Interface 0 (ESSI0) ........................................................................................1-11 1.9 Enhanced Synchronous Serial Interface 1 (ESSI1) ........................................................................................1-12 1.10 Serial Communication Interface (SCI) ...........................................................................................................1-14 1.11 Timers .............................................................................................................................................................1-15 1.12 JTAG and OnCE Interface ..............................................................................................................................1-16 Chapter 2 Specifications 2.1 Maximum Ratings.............................................................................................................................................2-1 2.3 Thermal Characteristics ....................................................................................................................................2-2 2.4 DC Electrical Characteristics............................................................................................................................2-2 2.5 AC Electrical Characteristics............................................................................................................................2-3 Chapter 3 Packaging 3.1 TQFP Package Description...............................................................................................................................3-2 3.2 TQFP Package Mechanical Drawing................................................................................................................3-9 3.3 MAP-BGA Package Description ....................................................................................................................3-10 3.4 MAP-BGA Package Mechanical Drawing .....................................................................................................3-18 Chapter 4 Design Considerations 4.1 Thermal Design Considerations........................................................................................................................4-1 4.2 Electrical Design Considerations......................................................................................................................4-2 4.3 Power Consumption Considerations.................................................................................................................4-3 4.4 PLL Performance Issues ...................................................................................................................................4-4 4.5 Input (EXTAL) Jitter Requirements .................................................................................................................4-5 Appendix A Power Consumption Benchmark Data Sheet Conventions OVERBAR Indicates a signal that is active when pulled low (For example, the RESET pin is active when low.) asserted Means that a high true (active high) signal is high or that a low true (active low) signal is low deasserted Means that a high true (active high) signal is low or that a low true (active low) signal is high Examples: Signal/Symbol Logic State Signal State Voltage PIN V /V True Asserted IL OL PIN V /V False Deasserted IH OH PIN V /V True Asserted IH OH PIN V /V False Deasserted IL OL Note: Values for V , V , V , and V are defined by individual product specifications. IL OL IH OH DSP56303 Technical Data, Rev. 11 ii Freescale Semiconductor