DSP56311 Freescale Semiconductor Rev. 8, 2/2005 Technical Data DSP56311 24-Bit Digital Signal Processor 3 16 6 6 Memory Expansion Area The DSP56311 is intended for applications requiring a Program RAM large amount of internal Triple SCI HI08 ESSI EFCOP 32 K 24 bits Timer or X Data Y Data memory, such as networking 31 K 24 bits RAM RAM and 48 K 24 bits 48 K 24 bits and wireless infrastructure Instruction Cache applications. The onboard 1024 24 bits Peripheral EFCOP can accelerate Expansion Area general filtering applications, YAB Address External XAB such as echo-cancellation 18 Generation Address Unit PAB Bus applications, correlation, and Address Six Channel DAB Switch DMA Unit general-purpose convolution- External 24-Bit Bus 13 based algorithms. Interface Bootstrap DSP56300 and ROM I - Cache Control Core Control DDB External YDB Internal 24 Whats New Data XDB Data Bus Rev. 8 includes the following Bus PDB Switch Data GDB Switch changes: Adds lead-free packaging and Power Management part numbers. Data ALU 5 Program Program Program Clock + 24 24 56 56-bit MAC JTAG PLL Interrupt Decode Address Generator Two 56-bit Accumulators Controller Controller Generator OnCE 56-bit Barrel Shifter DE EXTAL MODA/IRQA XTAL MODB/IRQB PCAP RESET MODC/IRQC PINIT/NMI MODD/IRQD Figure 1. DSP56311 Block Diagram The Freescale DSP56311, a member of the DSP56300 DSP family, supports network applications with general filtering operations. The Enhanced Filter Coprocessor (EFCOP) executes filter algorithms in parallel with core operations enhancing signal quality with no impact on channel throughput or total channels supported. The result is increased overall performance. Like the other DSP56300 family members, the DSP56311 uses a high-performance, single-clock-cycle-per- instruction engine (DSP56000 code-compatible), a barrel shifter, 24-bit addressing, an instruction cache, and a direct memory access (DMA) controller (see Figure 1). The DSP56311 performs at up to 150 million multiply-accumulates per second (MMACS), attaining up to 300 MMACS when the EFCOP is in use. It operates with an internal 150 MHz clock with a 1.8 volt core and independent 3.3 volt input/output (I/O) power. Freescale Semiconductor, Inc., 1999, 2005. All rights reserved. PIO EB PM EB XM EB YM EBTable of Contents Data Sheet Conventions.......................................................................................................................................ii Features...............................................................................................................................................................iii Target Applications .............................................................................................................................................iv Product Documentation ......................................................................................................................................iv Chapter 1 Signals/Connections 1.1 Power ................................................................................................................................................................1-3 1.2 Ground ..............................................................................................................................................................1-3 1.3 Clock.................................................................................................................................................................1-3 1.5 External Memory Expansion Port (Port A) ......................................................................................................1-4 1.6 Interrupt and Mode Control ..............................................................................................................................1-7 1.7 Host Interface (HI08)........................................................................................................................................1-8 1.8 Enhanced Synchronous Serial Interface 0 (ESSI0) ........................................................................................1-11 1.9 Enhanced Synchronous Serial Interface 1 (ESSI1) ........................................................................................1-12 1.10 Serial Communication Interface (SCI) ...........................................................................................................1-13 1.11 Timers .............................................................................................................................................................1-14 1.12 JTAG and OnCE Interface ..............................................................................................................................1-15 Chapter 2 Specifications 2.1 Maximum Ratings.............................................................................................................................................2-1 2.2 Thermal Characteristics ....................................................................................................................................2-2 2.3 DC Electrical Characteristics............................................................................................................................2-3 2.4 AC Electrical Characteristics............................................................................................................................2-4 Chapter 3 Packaging 3.1 Package Description .........................................................................................................................................3-2 3.2 MAP-BGA Package Mechanical Drawing .....................................................................................................3-10 Chapter 4 Design Considerations 4.1 Thermal Design Considerations........................................................................................................................4-1 4.2 Electrical Design Considerations......................................................................................................................4-2 4.3 Power Consumption Considerations.................................................................................................................4-3 4.4 PLL Performance Issues ...................................................................................................................................4-4 4.5 Input (EXTAL) Jitter Requirements .................................................................................................................4-6 Appendix A Power Consumption Benchmark Data Sheet Conventions OVERBAR Indicates a signal that is active when pulled low (For example, the RESET pin is active when low.) asserted Means that a high true (active high) signal is high or that a low true (active low) signal is low deasserted Means that a high true (active high) signal is low or that a low true (active low) signal is high Examples: Signal/Symbol Logic State Signal State Voltage PIN V /V True Asserted IL OL PIN V /V False Deasserted IH OH PIN V /V True Asserted IH OH PIN V /V False Deasserted IL OL Note: Values for V , V , V , and V are defined by individual product specifications. IL OL IH OH DSP56311 Technical Data, Rev. 8 ii Freescale Semiconductor