Document Number: DSP56362 Freescale Semiconductor Rev. 4, 08/2006 Technical Data DSP56362 24-Bit Audio Digital Signal Processor Contents 1 Overview 1 Overview 1-1 Freescale Semiconductor, Inc. designed the DSP56362 2 Signal/Connection Descriptions . 2-1 to support digital audio applications requiring digital 3 Specifications 3-1 4 Packaging . 4-1 audio compression and decompression, sound field 5 Design Considerations 5-1 processing, acoustic equalization, and other digital audio 6 Ordering Information 6-1 algorithms. The DSP56362 uses the high performance, A Power Consumption Benchmark A-1 single-clock-per-cycle DSP56300 core family of B IBIS Model . B-1 programmable CMOS digital signal processors (DSPs) combined with the audio signal processing capability of the Freescale Symphony DSP family, as shown in Figure 1-1. This design provides a two-fold performance increase over Freescales popular Symphony family of DSPs while retaining code compatibility. Significant architectural enhancements include a barrel shifter, 24-bit addressing, instruction cache, and direct memory access (DMA). The DSP56362 offers 100 million instructions per second (MIPS) using an internal 100 MHz clock at 3.3 V. This document contains information on a new product. Specifications and information herein are subject to change without notice. Freescale Semiconductor, Inc., 2006. All rights reserved.Overview Data Sheet Conventions This data sheet uses the following conventions: OVERBAR Used to indicate a signal that is active when pulled low (For example, the RESET pin is active when low.) asserted Means that a high true (active high) signal is high or that a low true (active low) signal is low deasserted Means that a high true (active high) signal is low or that a low true (active low) signal is high Examples: Signal/Symbol Logic State Signal State Voltage* PIN True Asserted V / V IL OL PIN False Deasserted V / V IH OH PIN True Asserted V / V IH OH PIN False Deasserted V / V IL OL Note: *Values for V , V , V , and V are defined by individual product specifications. IL OL IH OH 2 16 12 5 Program RAM/ Y Data X Data Instruction Host DAX RAM RAM Triple ESAI SHI Cache Interface 5632 24 (SPDIF) 3072 24 5632 Timer Memory ROM Program ROM 24 Expansion 30K 24 6144 ROM Area Bootstrap ROM 24 6144 24 192 24 Peripheral Expansion Area YAB 18 Address External XAB Generation Address Unit PAB Bus Address Switch Six Channel DAB DMA Unit DRAM/SRAM 24-Bit Bus 11 Interface DSP56300 & Control Core I - Cache Control DDB External YDB 24 Internal Data Bus XDB Data Switch Data PDB Bus GDB Switch Power EXTAL Clock Mngmnt. Data ALU 6 Generator Program Program Program + 24 24 56 56-bit MAC JTAG Interrupt Decode Address Two 56-bit Accumulators PLL Controller Controller Generator OnCE 56-bit Barrel Shifter CLKOUT MODA/IRQA MODB/IRQB RESET MODC/IRQC MODD/IRQD AA0456G PINIT/NMI Figure 1-1 DSP56362 Block Diagram DSP56362 Technical Data, Rev. 4 1-2 Freescale Semiconductor PIO EB PM EB XM EB YM EB