DSP56321 Freescale Semiconductor Rev. 11, 2/2005 Technical Data DSP56321 24-Bit Digital Signal Processor 3 16 6 6 The DSP56321 is intended Memory Expansion Area for applications requiring a Program large amount of internal RAM Triple 32 K 24 bits SCI HI08 ESSI EFCOP memory, such as networking Timer or X Data Y Data 31 K 24 bits RAM RAM and wireless infrastructure and 80 K 24 bits 80 K 24 bits Instruction applications. The onboard Cache 1024 24 bits EFCOP can accelerate Peripheral general filtering applications, Expansion Area YAB such as echo-cancellation Address External XAB 18 Generation Address applications, correlation, and Unit PAB Bus Address DAB Switch Six Channel general-purpose convolution- DMA Unit External based algorithms. 24-Bit Bus 10 Bootstrap Interface DSP56300 and ROM I - Cache Control Core Control DDB Whats New External YDB Internal 24 Data XDB Rev. 11 includes the following Data Bus PDB Bus changes: Switch Data Switch GDB Adds lead-free packaging and Power part numbers. Management Data ALU 5 Program Program Program Clock + 24 24 56 56-bit MAC PLL JTAG Interrupt Decode Address Generator Two 56-bit Accumulators Controller Controller Generator OnCE 56-bit Barrel Shifter DE EXTAL MODA/IRQA XTAL MODB/IRQB RESET MODC/IRQC PINIT/NMI MODD/IRQD Figure 1. DSP56321 Block Diagram The Freescale DSP56321, a member of the DSP56300 DSP family, supports networking, security encryption, and home entertainment using a high-performance, single-clock-cycle-per- instruction engine (DSP56000 code- compatible), a barrel shifter, 24-bit addressing, an instruction cache, and a direct memory access (DMA) controller (see Figure 1). The DSP56321 offers 275 million multiply- accumulates per second (MMACS) performance, attaining 550 MMACS when the EFCOP is in use. It operates with an internal 275 MHz clock with a 1.6 volt core and independent 3.3 volt input/output (I/O) power. By operating in parallel with the core, the EFCOP provides overall enhanced performance and signal quality with no impact on channel throughput or total channel support. This device is pin-compatible with the Freescale DSP56303, DSP56L307, DSP56309, and DSP56311. Freescale Semiconductor, Inc., 2001, 2005. All rights reserved. PIO EB PM EB XM EB YM EBTable of Contents Data Sheet Conventions.......................................................................................................................................ii Features...............................................................................................................................................................iii Target Applications .............................................................................................................................................iv Product Documentation .......................................................................................................................................v Chapter 1 Signals/Connections 1.1 Power ................................................................................................................................................................1-3 1.2 Ground ..............................................................................................................................................................1-3 1.3 Clock.................................................................................................................................................................1-3 1.4 External Memory Expansion Port (Port A) ......................................................................................................1-4 1.5 Interrupt and Mode Control ..............................................................................................................................1-6 1.6 Host Interface (HI08)........................................................................................................................................1-7 1.7 Enhanced Synchronous Serial Interface 0 (ESSI0) ........................................................................................1-10 1.8 Enhanced Synchronous Serial Interface 1 (ESSI1) ........................................................................................1-11 1.9 Serial Communication Interface (SCI) ...........................................................................................................1-12 1.10 Timers .............................................................................................................................................................1-13 1.11 JTAG and OnCE Interface ..............................................................................................................................1-14 Chapter 2 Specifications 2.1 Maximum Ratings.............................................................................................................................................2-1 2.2 Thermal Characteristics ....................................................................................................................................2-2 2.3 DC Electrical Characteristics............................................................................................................................2-2 2.4 AC Electrical Characteristics............................................................................................................................2-3 Chapter 3 Packaging 3.1 Package Description .........................................................................................................................................3-2 3.2 MAP-BGA Package Mechanical Drawing .....................................................................................................3-10 Chapter 4 Design Considerations 4.1 Thermal Design Considerations........................................................................................................................4-1 4.2 Electrical Design Considerations......................................................................................................................4-2 4.3 Power Consumption Considerations.................................................................................................................4-3 4.4 Input (EXTAL) Jitter Requirements .................................................................................................................4-4 Appendix A Power Consumption Benchmark Data Sheet Conventions OVERBAR Indicates a signal that is active when pulled low (For example, the RESET pin is active when low.) asserted Means that a high true (active high) signal is high or that a low true (active low) signal is low deasserted Means that a high true (active high) signal is low or that a low true (active low) signal is high Examples: Signal/Symbol Logic State Signal State Voltage PIN V /V True Asserted IL OL PIN V /V False Deasserted IH OH PIN V /V True Asserted IH OH PIN V /V False Deasserted IL OL Note: Values for V , V , V , and V are defined by individual product specifications. IL OL IH OH DSP56321 Technical Data, Rev. 11 ii Freescale Semiconductor