Document Number: DSP56366 Freescale Semiconductor Rev. 3.1, 1/2007 Data Sheet: Technical Data DSP56366 24-Bit Audio Digital Signal Processor Contents 1 Overview 1 Overview 1-1 The DSP56366 supports digital audio applications 2 Signal/Connection Descriptions . 2-1 requiring sound field processing, acoustic equalization, 3 Specifications 3-1 4 Packaging . 4-1 and other digital audio algorithms. The DSP56366 uses 5 Design Considerations 5-1 the high performance, single-clock-per-cycle DSP56300 6 Ordering Information 6-1 core family of programmable CMOS digital signal A Power Consumption Benchmark A-1 processors (DSPs) combined with the audio signal processing capability of the Freescale Symphony DSP family, as shown in Figure 1-1. This design provides a two-fold performance increase over Freescales popular 56000 Symphony family of DSPs while retaining code compatibility. Significant architectural enhancements include a barrel shifter, 24-bit addressing, instruction cache, and direct memory access (DMA). The DSP56366 offers 120 million instructions per second (MIPS) using an internal 120 MHz clock at 3.3 V. This document contains information on a new product. Specifications and information herein are subject to change without notice. Freescale Semiconductor, Inc., 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007. All rights reserved.Overview Data Sheet Conventions This data sheet uses the following conventions: OVERBAR Used to indicate a signal that is active when pulled low (For example, the RESET pin is active when low.) asserted Means that a high true (active high) signal is high or that a low true (active low) signal is low deasserted Means that a high true (active high) signal is low or that a low true (active low) signal is high Examples: Signal/Symbol Logic State Signal State Voltage* PIN True Asserted V / V IL OL PIN False Deasserted V / V IH OH PIN True Asserted V / V IH OH PIN False Deasserted V / V IL OL Note: *Values for V , V , V , and V are defined by individual product specifications. IL OL IH OH 4 8 2 16 5 1 6 MEMORY EXPANSION AREA PROGRAM DAX RAM/INSTR. HOST SHI TRIPLE ESAI X MEMORY Y MEMORY (SPDIF Tx.) CACHE INTER- INTER- TIMER INTER- RAM RAM INTER- 3K x 24 FACE FACE FACE 13K X 24 7K X 24 FACE PROGRAM ROM ROM ROM 40K x 24 32K x 24 8K x 24 ESAI 1 Bootstrap ROM 192 x 24 PERIPHERAL EXPANSION AREA ADDRESS YAB EXTERNAL GENERATION 18 XAB ADDRESS UNIT PAB BUS DAB ADDRESS SIX CHANNELS SWITCH DMA UNIT 24-BIT DRAM & DSP56300 SRAM BUS 10 Core INTERFACE & CONTROL I - CACHE DDB YDB EXTERNAL 24 INTERNAL XDB DATA BUS DATA SWITCH PDB BUS DATA SWITCH GDB POWER MNGMNT PLL DATA ALU + -> PROGRAM 24X24 56 56-BIT MAC PROGRAM PROGRAM 4 DECODE TWO 56-BIT INTERRUPT ADDRESS JTAG CLOCK CONTROLLER CONTROLLER GENERATOR ACCUMULATORS GENERATOR BARREL SHIFTER OnCE EXTAL 24 BITS BUS MODA/IRQA MODB/IRQB RESET MODC/IRQC PINIT/NMI MODD/IRQD Figure 1-1 DSP56366 Block Diagram DSP56366 Technical Data, Rev. 3.1 1-2 Freescale Semiconductor PIO EB PM EB XM EB YM EB