Document Number: DSP56364 Freescale Semiconductor Rev. 4.1, 10/2007 Technical Data DSP56364 24-Bit Audio Digital Signal Processor Contents 1 Overview 1 Overview 1-1 The DSP56364 supports digital audio applications 2 Signal/Connection Descriptions . 2-1 requiring sound field processing, acoustic equalization, 3 Specifications 3-1 4 Packaging . 4-1 and other digital audio algorithms. The DSP56364 uses 5 Design Considerations 5-1 the high performance, single-clock-per-cycle DSP56300 6 Ordering Information 6-1 core family of programmable CMOS digital signal A IBIS Model . A-1 processors (DSPs) combined with the audio signal processing capability of the Freescale Symphony DSP family, as shown in Figure 1-1. This design provides a two-fold performance increase over Freescales popular Symphony family of DSPs while retaining code compatibility. Significant architectural enhancements include a barrel shifter, 24-bit addressing, instruction cache, and direct memory access (DMA). The DSP56364 offers 100 million instructions per second (MIPS) using an internal 100 MHz clock at 3.3 V. Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Freescale Semiconductor, Inc., 2006, 2007. All rights reserved.Overview Data Sheet Conventions This data sheet uses the following conventions: OVERBAR Used to indicate a signal that is active when pulled low (For example, the RESET pin is active when low.) asserted Means that a high true (active high) signal is high or that a low true (active low) signal is low deasserted Means that a high true (active high) signal is low or that a low true (active low) signal is high Examples: Signal/Symbol Logic State Signal State Voltage* PIN True Asserted V / V IL OL PIN False Deasserted V / V IH OH PIN True Asserted V / V IH OH PIN False Deasserted V / V IL OL Note: *Values for V , V , V , and V are defined by individual product specifications. IL OL IH OH 4 12 5 PROGRAM RAM X Y 0.5K x 24 MEMORY MEMORY SHI GPIO ESAI RAM RAM PROGRAM ROM 1K X 24 1.5K X 24 8K x 24 PERIPHERAL Bootstrap ROM MEMORY EXPANSION 192 x 24 EXPANSION AREA AREA ADDRESS ADDRESS YAB EXTERNAL GENERATION UNIT XAB 18 ADDRESS PAB BUS SIX CHANNELS DAB SWITCH DMA UNIT 24-BIT CONTROL DRAM & SRAM 6 DSP56300 BUS INTERFACE CORE DDB YDB DATA EXTERNAL INTERNAL 8 DATA BUS DATA BUS XDB SWITCH SWITCH PDB GDB POWER MGMT DATA ALU PLL PROGRAM PROGRAM + PROGRAM 24 X 24 56 56-BIT MAC 4 JTAG DECODE INTERRUPT ADDRESS TWO 56-BIT CONT GEN ACCUMULATORS CLOCK CONT OnCE BARREL SHIFTER GEN EXTAL MODA/IRQA 24 BITS BUS RESET MODB/IRQB PINIT/NMI MODD/IRQD Figure 1-1 DSP56364 Block Diagram DSP56364 Technical Data, Rev. 4.1 1-2 Freescale Semiconductor PIO EB PM EB XM EB YM EB