HEF4071BP,652 NXP

HEF4071B Quad 2-input OR gate Rev. 7 15 November 2011 Product data sheet 1. General description The HEF4071B is a quad 2-input OR gate. The outputs are fully buffered for highest noise immunity and pattern insensitivity to output impedance variations. It operates over a recommended V power supply range of 3 V to 15 V referenced to V DD SS (usually ground). Unused inputs must be connected to V , V , or another input. DD SS 2. Features and benefits Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Inputs and outputs are protected against electrostatic effects Specified from 40 C to +85 C and 40 C to +125 C Complies with JEDEC standard JESD 13-B 3. Ordering information Table 1. Ordering information All types operate from 40 C to +125 C. Type number Package Name Description Version HEF4071BP DIP14 plastic dual in-line package 14 leads (300 mil) SOT27-1 HEF4071BT SO14 plastic small outline package 14 leads body width 3.9 mm SOT108-1 4. Functional diagram 1 1A 1Y 3 2 1B 5 2A 2Y 4 6 2B 8 3A 3Y 10 9 3B 12 4A 4Y 11 13 4B nA nY nB 001aaj110 001aaj108 Fig 1. Functional diagram Fig 2. Logic diagram (one gate)HEF4071B NXP Semiconductors Quad 2-input OR gate 5. Pinning information 5.1 Pinning HEF4071B 1A 1 14 V DD 1B 2 13 4B 1Y 3 12 4A 2Y 4 11 4Y 5 10 2A 3Y 2B 6 9 3B V 7 8 3A SS 001aaj107 Fig 3. Pin configuration 5.2 Pin description Table 2. Pin description Symbol Pin Description 1A to 4A 1, 5, 8, 12 input 1B to 4B 2, 6, 9, 13 input 1Y to 4Y 3, 4, 10, 11 output V 7 ground (0 V) SS V 14 supply voltage DD 6. Functional description 1 Table 3. Function table Input Output nA nB nY LL L LH H HL H HH H 1 H = HIGH voltage level L = LOW voltage level. HEF4071B All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved. Product data sheet Rev. 7 15 November 2011 2 of 12