HEF4520BP,652 NXP

HEF4520B Dual binary counter Rev. 6 18 November 2011 Product data sheet 1. General description The HEF4520B is a dual 4-bit internally synchronous binary counter. The counter has an active HIGH clock input (nCP0) and an active LOW clock input (nCP1), buffered outputs from all four bit positions (nQ0 to nQ3) and an active HIGH overriding asynchronous master reset input (nMR). The counter advances on either the LOW-to-HIGH transition of the nCP0 input if nCP1 is HIGH or the HIGH-to-LOW transition of the nCP1 input if nCP0 is LOW. Either nCP0 or nCP1 may be used as the clock input to the counter while the other clock input may be used as a clock enable input. Schmitt trigger action makes the clock input highly tolerant of slower clock rise and fall times. A HIGH on nMR resets the counter (nQ0 to nQ3 = LOW) independent of nCP0 and nCP1. It operates over a recommended V power supply range of 3 V to 15 V referenced to V DD SS (usually ground). Unused inputs must be connected to V , V , or another input. DD SS 2. Features and benefits Tolerant of slow clock rise and fall times Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Specified from 40 C to +85 C Complies with JEDEC standard JESD 13-B 3. Ordering information Table 1. Ordering information All types operate from 40 C to +85 C. Type number Package Name Description Version HEF4520BP DIP16 plastic dual in-line package 16 leads (300 mil) SOT38-4 HEF4520BT SO16 plastic small outline package 16 leads body width 3.9 mm SOT109-1HEF4520B NXP Semiconductors Dual binary counter 4. Functional diagram 1Q0 3 1 1CP0 1Q1 4 2 1CP1 1Q2 5 1Q3 6 7 1MR 2Q0 11 9 2CP0 2Q1 12 10 2CP1 2Q2 13 2Q3 14 15 2MR 001aae698 Fig 1. Functional diagram 123456789 10 11 12 13 14 15 16 17 18 nCP0 nCP1 nMR 123456789 10 11 12 13 14 15 01234 nQ0 nQ1 nQ2 nQ 3 001aae707 Fig 2. Timing diagram nQ0 nQ1 nQ2 nQ3 Q Q Q Q FF 1 FF 2 FF 3 FF 4 nCP1 T T T T Q Q Q Q CD CD CD CD nCP0 nMR 001aae705 Fig 3. Logic diagram for one counter HEF4520B All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved. Product data sheet Rev. 6 18 November 2011 2 of 14