I74F257AD,118 NXP

INTEGRATED CIRCUITS 74F257A Quad 2-line to 1-line selector/multiplexer, non-inverting (3-State) Product specification 1995 Mar 31 IC15 Data Handbook Philips SemiconductorsPhilips Semiconductors Product specification Quad 2-line to 1-line selector/multiplexer, non-inverting 74F257A (3-State) FEATURES PIN CONFIGURATION Industrial range available (40C to +85C) S 1 16 V CC Multifunction capability I0a 2 15 OE Non-inverting data path I1a 3 14 I0d 3-State outputs Ya 4 13 I1d See 74F258A for inverting version I0b 5 12 Yd I1b 6 11 I0c DESCRIPTION Yb 7 10 I1c The 74F257A has four identical 2-input multiplexers with 3-State outputs which select 4 bits of data from two sources uncer control of GND 8 9 Yc a common Select (S) input. The I0a inputs are selected when the common Select input is Low and the I1n inputs are selected when SF00673 the common Select input is High. Data appears at the outputs in true non-inverted form from the selected inputs. The 74F257A is the logic implementation of a 4-pole, 2-position switch where the position of the switch is determined by the logic levels supplied to the common Slect input. Outputs are forced to a high impedance off state when the Output Enable (OE) is High. All but one device must be in high TYPICAL TYPICAL SUPPLY CURRENT TYPE impedance state to avoid currents that would exceed the maximum PROPAGATION DELAY (TOTAL) rating if the outputs were tied together. Design of the Output Enable signals must ensure that there is no overlap when outputs of 3-state 74F257A 4.3ns 12mA devices were tied together. ORDERING INFORMATION ORDER CODE DRAWING DRAWING DESCRIPTION COMMERCIAL RANGE INDUSTRIAL RANGE NUMBER V = 5V 10%, T = 0C to +70C V = 5V 10%, T = 40C to +85C CC amb CC amb 16-pin plastic DIP N74F257AN I74F257AN SOT38-4 16-pin plastic SO N74F257AD I74F257AD SOT109-1 INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS DESCRIPTION 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW I0n, I1n Data inputs 1.0/1.0 20A/0.6mA S Common Select input 1.0/1.0 20A/0.6mA OE Output Enable input (active Low) 1.0/1.0 20A/0.6mA Ya Yd Data outputs 150/33 3.0mA/20mA NOTE: One (1.0) FAST unit load is defined as: 20A in the High state and 0.6mA in the Low state. LOGIC SYMBOL LOGIC SYMBOL (IEEE/IEC) 15 EN 2356 11 10 14 13 1 G1 2 MUX 1 4 I0a I1a I0b I1b I0c I1c I0d I1d 3 1 1 S 5 7 15 OE 6 10 Ya Yb Yc Yd 9 11 13 12 14 479 12 V = Pin 16 CC GND = Pin 8 SF00675 SF00674 2 1995 Mar 31 8530360 15059