DG429DN-E3 Vishay

DG428, DG429 Vishay Siliconix Single 8-Ch/Differential 4-Ch Latchable Analog Multiplexers FEATURES DESCRIPTION Halogen-free according to IEC 61249-2-21 The DG428, DG429 analog multiplexers have on-chip Definition address and control latches to simplify design in Low R : 55 DS(on) microprocessor based applications. Break-before-make Low Charge Injection: 1 pC switching action protects against momentary crosstalk of On-Board TTL Compatible Address Latches adjacent input signals. High Speed - t : 160 ns TRANS The DG428 selects one of eight single-ended inputs to a Break-Before-Make common output, while the DG429 selects one of four Low Power Consumption: 0.3 mW differential inputs to a common differential output. Compliant to RoHS Directive 2002/95/EC An on channel conducts current equally well in both directions. In the off state each channel blocks voltages up to BENEFITS the power supply rails. An enable (EN) function allows the Improved System Accuracy user to reset the multiplexer/demultiplexer to all switches off Microprocessor Bus Compatible for stacking several devices. All control inputs, address (A ) x Easily Interfaced and enable (EN) are TTL compatible over the full specified Reduced Crosstalk operating temperature range. High Throughput The silicon-gate CMOS process enables operation over a Improved Reliability wide range of supply voltages. The absolute maximum voltage rating is extended to 44 V. Additionally, single supply APPLICATIONS operation is also allowed and an epitaxial layer prevents Data Acquisition Systems latchup. Automatic Test Equipment On-board TTL-compatible address latches simplify the digital Avionics and Military Systems interface design and reduce board space in bus-controlled Communication Systems systems such as data acquisition systems, process controls, Microprocessor-Controlled Analog Systems avionics, and ATE. Medical Instrumentation FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION DG428 DG428 Dual-In-Line PLCC WR 1 18 RS 312 1 209 A 2 17 A 0 1 Latches EN 3 16 A 2 EN 4 18 A Latches 2 V- 5 17 GND Decoders/Drivers Decoders/Drivers V- GND 4 15 V+ S 6 16 1 S 5 14 V+ 1 S S 7 15 2 5 S S 6 13 2 5 S 8 14 S 3 6 S 7 12 S 3 6 9110 11 123 S 8 11 S 4 7 D910 S 8 Top View Top View Document Number: 70063 www.vishay.com S11-1350Rev. K, 04-Jul-11 1 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000 S A 4 0 WR D NC NC S RS 8 S A 7 1DG428, DG429 Vishay Siliconix FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION DG429 DG429 Dual-In-Line and SOIC PLCC WR RS 1 18 312 1 209 A A 0 1 2 17 EN Latches GND 3 16 EN 4 Latches 18 GND V- V 5 Decoders/Drivers 17 DD V- Decoders/Drivers V+ 4 15 S S 6 16 1b 1a S S 5 14 1a 1b S 7 15 S 2a 2b S S 2a 6 13 2b S 8 14 S 3a 3b S S 3a 7 12 3b 9110 11 123 S S 8 11 4a 4b D910 D a b Top View Top View TRUTH TABLE - DG428 TRUTH TABLE - DG429 8-Channel Single-Ended Multiplexer Differential 4-Channel Multiplexer A A A A A EN WR RS On Switch EN WR RS On Switch 2 1 0 1 0 Latching Latching Maintains previous Maintains previous X X X X 1 X X X 1 switch condition switch condition Reset Reset None (latches None (latches X X X X X 0 X X X X 0 cleared) cleared) Transparent Operation Transparent Operation X X X 0 0 1 None X X 0 0 1 None 0 0 0 1 0 1 1 0 0 1 0 1 1 0 0 1 1 0 1 2 0 1 1 0 1 2 0 1 0 1 0 1 3 1 0 1 0 1 3 0 1 1 1 0 1 4 1 1 1 0 1 4 1 0 0 1 0 1 5 Logic0 = V 0.8 V AL Logic1 = V 2.4 V 1 0 1 1 0 1 6 AH X = Dont Care 1 1 0 1 0 1 7 1 1 1 1 0 1 8 ORDERING INFORMATION - DG428 ORDERING INFORMATION - DG429 Temp Range Package Part Number Temp Range Package Part Number DG428DJ DG429DJ 18-pin Plastic DIP 18-pin Plastic DIP DG428DJ-E3 DG429DJ-E3 - 40 C to 85 C DG428DN DG429DN 20-pin PLCC - 40 C to 85 C 20-pin PLCC DG428DN-E3 DG429DN-E3 DG429DW 18-pin Widebody SOIC DG429DW-E3 www.vishay.com Document Number: 70063 2 S11-1350Rev. K, 04-Jul-11 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000 S A 4a 0 D WR a NC NC D RS b S A 4b 1