LPC11E1x 32-bit ARM Cortex-M0 microcontroller up to 32 kB flash up to 10 kB SRAM and 4 kB EEPROM USART Rev. 1.1 24 September 2013 Product data sheet 1. General description The LPC11E1x are an ARM Cortex-M0 based, low-cost 32-bit MCU family, designed for 8/16-bit microcontroller applications, offering performance, low power, simple instruction set and memory addressing together with reduced code size compared to existing 8/16-bit architectures. The LPC11E1x operate at CPU frequencies of up to 50 MHz. The peripheral complement of the LPC11E1x includes up to 32 kB of flash memory, up to 2 10 kB of SRAM data memory and 4 kB EEPROM, one Fast-mode Plus I C-bus interface, one RS-485/EIA-485 USART with support for synchronous mode and smart card interface, two SSP interfaces, four general-purpose counter/timers, a 10-bit ADC, and up to 54 general-purpose I/O pins. 2. Features and benefits System: ARM Cortex-M0 processor, running at frequencies of up to 50 MHz. ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC). Non-Maskable Interrupt (NMI) input selectable from several input sources. System tick timer. Memory: Up to 32 kB on-chip flash program memory. Up to 4 kB on-chip EEPROM data memory byte erasable and byte programmable. Up to 10 kB SRAM data memory. 16 kB boot ROM including 32-bit integer divide routines and power profiles. In-System Programming (ISP) and In-Application Programming (IAP) for flash and EEPROM via on-chip bootloader software. Debug options: Standard JTAG test interface for BSDL. Serial Wire Debug.LPC11E1x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Digital peripherals: Up to 54 General-Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors, repeater mode, and open-drain mode. Up to 8 GPIO pins can be selected as edge and level sensitive interrupt sources. Two GPIO grouped interrupt modules enable an interrupt based on a programmable pattern of input states of a group of GPIO pins. High-current source output driver (20 mA) on one pin. High-current sink driver (20 mA) on true open-drain pins. Four general-purpose counter/timers with a total of up to 8 capture inputs and 13 match outputs. Programmable Windowed WatchDog Timer (WWDT) with a dedicated, internal low-power WatchDog Oscillator (WDO). Analog peripherals: 10-bit ADC with input multiplexing among eight pins. Serial interfaces: USART with fractional baud rate generation, internal FIFO, a full modem control handshake interface, and support for RS-485/9-bit mode and synchronous mode. USART supports an asynchronous smart card interface (ISO 7816-3). Two SSP controllers with FIFO and multi-protocol capabilities. 2 2 I C-bus interface supporting the full I C-bus specification and Fast-mode Plus with a data rate of up to 1 Mbit/s with multiple address recognition and monitor mode. Clock generation: Crystal Oscillator with an operating range of 1 MHz to 25 MHz (system oscillator). 12 MHz high-frequency Internal RC oscillator (IRC) that can optionally be used as a system clock. Internal low-power, low-frequency WatchDog Oscillator (WDO) with programmable frequency output. PLL allows CPU operation up to the maximum CPU rate with the system oscillator or the IRC as clock sources. Clock output function with divider that can reflect the crystal oscillator, the main clock, the IRC, or the watchdog oscillator. Power control: Integrated PMU (Power Management Unit) to minimize power consumption during Sleep, Deep-sleep, Power-down, and Deep power-down modes. Power profiles residing in boot ROM allow optimized performance and minimized power consumption for any given application through one simple function call. Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep power-down. Processor wake-up from Deep-sleep and Power-down modes via reset, selectable GPIO pins, or a watchdog interrupt. Processor wake-up from Deep power-down mode using one special function pin. Power-On Reset (POR). Brownout detect with four separate thresholds for interrupt and forced reset. LPC11E1X All information provided in this document is subject to legal disclaimers. NXP B.V. 2013. All rights reserved. Product data sheet Rev. 1.1 24 September 2013 2 of 62