LPC18S50/S30/S10 32-bit ARM Cortex-M3 flashless MCU with security features up to 200 kB SRAM Ethernet, two HS USB, LCD, EMC, AES Rev. 1.3 10 January 2020 Product data sheet 1. General description The LPC18S50/S30/S10 are ARM Cortex-M3 based microcontrollers with security features for embedded applications. The ARM Cortex-M3 is a next generation core that offers system enhancements such as low power consumption, enhanced debug features, and a high level of support block integration. The LPC18S50/S30/S10 operate at CPU frequencies of up to 180 MHz. The ARM Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals. The ARM Cortex-M3 CPU also includes an internal prefetch unit that supports speculative branching. The LPC18S50/S30/S10 include up to 200 kB of on-chip SRAM, security features with AES engine, a quad SPI Flash Interface (SPIFI), a State Configurable Timer/PWM (SCTimer/PWM) subsystem, two High-speed USB controllers, Ethernet, LCD, an external memory controller, and multiple digital and analog peripherals. See Section 17 References for additional documentation. 2. Features and benefits Processor core ARM Cortex-M3 processor, running at frequencies of up to 180 MHz. ARM Cortex-M3 built-in Memory Protection Unit (MPU) supporting eight regions. ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC). Non-maskable Interrupt (NMI) input. JTAG and Serial Wire Debug, serial trace, eight breakpoints, and four watch points. Enhanced Trace Module (ETM) and Enhanced Trace Buffer (ETB) support. System tick timer. On-chip memory 200 kB SRAM for code and data use. Multiple SRAM blocks with separate bus access. 64 kB ROM containing boot code and on-chip software drivers. 64 bit One-Time Programmable (OTP) memory for general-purpose use. Two banks (256 bit total) One-Time Programmable (OTP) memory for AES key storage One bank can store an encrypted key for decoding the boot image. AES engine for encryption and decryption of the boot image and data with DMA support and programmable via a ROM-based API. Clock generation unit NXP Semiconductors LPC18S50/S30/S10 32-bit ARM Cortex-M3 microcontroller Crystal oscillator with an operating range of 1 MHz to 25 MHz. 12 MHz internal RC oscillator trimmed to 1.5 % accuracy over temperature and voltage. Ultra-low power RTC crystal oscillator. Three PLLs allow CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. The second PLL is dedicated to the High-speed USB, the third PLL can be used as audio PLL. Clock output. Configurable digital peripherals: State Configurable Timer (SCTimer/PWM) subsystem on AHB. Global Input Multiplexer Array (GIMA) allows to cross-connect multiple inputs and outputs to event driven peripherals like timers, SCTimer/PWM, and ADC0/1. Serial interfaces: Quad SPI Flash Interface (SPIFI) with 1-, 2-, or 4-bit data at rates of up to 52 MB per second. 10/100T Ethernet MAC with RMII and MII interfaces and DMA support for high throughput at low CPU load. Support for IEEE 1588 time stamping/advanced time stamping (IEEE 1588-2008 v2). One High-speed USB 2.0 Host/Device/OTG interface with DMA support and on-chip high-speed PHY (USB0). One High-speed USB 2.0 Host/Device interface with DMA support, on-chip full-speed PHY and ULPI interface to an external high-speed PHY (USB1). USB interface electrical test software included in ROM USB stack. Four 550 UARTs with DMA support: one UART with full modem interface one UART with IrDA interface three USARTs support UART synchronous mode and a smart card interface conforming to ISO7816 specification. Up to two C CAN 2.0B controllers with one channel each. Use of C CAN controller excludes operation of all other peripherals connected to the same bus bridge See Figure 1 and Ref. 2. Two SSP controllers with FIFO and multi-protocol support. Both SSPs with DMA support. 2 One Fast-mode Plus I C-bus interface with monitor mode and with open-drain I/O 2 pins conforming to the full I C-bus specification. Supports data rates of up to 1 Mbit/s. 2 One standard I C-bus interface with monitor mode and standard I/O pins. 2 Two I S interfaces with DMA support, each with one input and one output. Digital peripherals: External Memory Controller (EMC) supporting external SRAM, ROM, NOR flash, and SDRAM devices. LCD controller with DMA support and a programmable display resolution of up to 1024 H 768 V. Supports monochrome and color STN panels and TFT color panels supports 1/2/4/8 bpp Color Look-Up Table (CLUT) and 16/24-bit direct pixel mapping. Secure Digital Input Output (SD/MMC) card interface. Eight-channel General-Purpose DMA controller can access all memories on the AHB and all DMA-capable AHB slaves. LPC18S50 S30 S10 All information provided in this document is subject to legal disclaimers. NXP Semiconductors N.V. 2020. All rights reserved. Product data sheet Rev. 1.3 10 January 2020 2 of 152