LPC54101J256BD64QL NXP

LPC5410x 32-bit ARM Cortex-M4/M0+ MCU 104 kB SRAM 512 kB flash, 3 x I2C, 2 x SPI, 4 x USART, 32-bit counter/ timers, SCTimer/PWM, 12-bit 5.0 Msamples/sec ADC Rev. 2.12 3 September 2020 Product data sheet 1. General description The LPC5410x are ARM Cortex-M4 based microcontrollers for embedded applications. These devices include: Optional ARM Cortex-M0+ coprocessor. 104 kB of on-chip SRAM. Up to 512 kB on-chip flash. State-Configurable Timer with PWM capabilities (SCTimer/PWM). RTC/alarm timer. 24-bit Multi-Rate Timer (MRT). 12-bit 5.0 Msamples/sec ADC. Repetitive Interrupt Timer (RIT). Windowed Watchdog Timer (WWDT). Two SPIs. 2 Three Fast-mode plus I C-bus interfaces with high-speed slave mode. Four USARTs. Five general-purpose timers. The ARM Cortex-M4 is a 32-bit core that offers system enhancements such as low power consumption, enhanced debug features, and a high level of support block integration. The ARM Cortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals, and includes an internal prefetch unit that supports speculative branching. The ARM Cortex-M4 supports single-cycle digital signal processing and SIMD instructions. A hardware floating-point unit is integrated in the core. The ARM Cortex-M0+ coprocessor is an energy-efficient and easy-to-use 32-bit core which is code and tool-compatible with the Cortex-M4 core. The Cortex-M0+ coprocessor offers up to 150 MHz performance with a simple instruction set and reduced code size. In LPC5410x, the Cortex-M0 coprocessor hardware multiply is implemented as a 32-cycle iterative multiplier. NXP Semiconductors LPC5410x 32-bit ARM Cortex-M4/M0+ microcontroller 2. Features and benefits Dual processor cores: ARM Cortex-M4 and ARM Cortex-M0+. The M0+ core runs at the same frequency as the M4 core. Both cores operate up to a maximum frequency of 150 MHz. ARM Cortex-M4 core (version r0p1): ARM Cortex-M4 processor, running at a frequency of up to 150 MHz, using the same clock as the Cortex-M4. Floating Point Unit (FPU) and Memory Protection Unit (MPU). ARM Cortex-M4 built-in Nested Vectored Interrupt Controller (NVIC). Non-maskable Interrupt (NMI) input with a selection of sources. Serial Wire Debug with eight breakpoints and four watch points. Includes Serial Wire Output for enhanced debug capabilities. System tick timer. ARM Cortex-M0+ core (version r0p1): ARM Cortex-M0+ processor, running at a frequency of up to 150 MHz. ARM Cortex-M0+ built-in Nested Vectored Interrupt Controller (NVIC). Non-maskable Interrupt (NMI) input with a selection of sources. Serial Wire Debug with four breakpoints and two watch points. System tick timer. On-chip memory: Up to 512 kB on-chip flash program memory with flash accelerator and 256 byte page erase and write. 104 kB total SRAM composed of: Up to 96 kB contiguous main SRAM. An additional 8 kB SRAM. ROM API support: Flash In-Application Programming (IAP) and In-System Programming (ISP). Power control API. Serial interfaces: Four USART interfaces with synchronous mode and 32 kHz mode for wake-up from deep sleep and power down modes. The USARTs have FIFO support from the System FIFO and share a fractional baud-rate generator. Two SPI interfaces, each with four slave selects and flexible data configuration. The SPIs have FIFO support from the System FIFO. The slave function is able to wake up the device from deep sleep and power down modes. 2 Three I C-bus interfaces supporting fast mode and Fast-mode Plus with data rates of up to 1Mbit/s and with multiple address recognition and monitor mode. Each 2 I C-bus interface also supports High Speed Mode (3.4 Mbit/s) as a slave. The slave function is able to wake up the device from deep sleep and power down modes. Digital peripherals: DMA controller with 22 channels and 20 programmable triggers, able to access all memories and DMA-capable peripherals. LPC5410x All information provided in this document is subject to legal disclaimers. NXP B.V. 2020. All rights reserved. Product data sheet Rev. 2.12 3 September 2020 2 of 95