Document Number LS1012A NXP Semiconductors Rev. 2, 01/2019 Data Sheet: Technical Data LS1012A QorIQ LS1012A Data Sheet Features Additional peripheral interfaces One Quad Serial Peripheral Interface (QSPI) LS1012A contains one 64-bit Arm Cortex-A53 controller for serial Flash core processor with the following capabilities: One Serial Peripheral Interface (SPI) controller 256 kB L2 cache w/ECC Two enhanced secure digital host controllers (SD, Neon SIMD Co-processor SDIO, eMMC) Arm v8 Cryptography Extensions Two I2C controllers Single-threaded cores with 32 KB L1 data cache and One 16550 compliant DUART (two UART 32 KB L1 instruction cache, and both Neon and interfaces) Precision Floating Point module support General Purpose IO (GPIO) One 16-bit DDR3L SDRAM memory controller Two Flextimers Up to 1.0 GT/s Five Synchronous Audio Interfaces (SAI) Supports 16-bit operation (no ECC support) QorIQ Platforms Trust Architecture Support for x8 and x16 devices Debug supporting run control, data acquisition, high- Packet Forwarding Engine (PFE) speed trace, and performance/event monitoring Cryptography acceleration (SEC) Pre-boot loader (PBL) provides pre-boot initialization Three SerDes lanes and RCW loading capabilities Two SerDes PLLs supported for usage by any Single-source clocking solution enabling generation of SerDes data lane core, platform, DDR, SerDes, and USB clocks from a Support for up to 6 Gbit/s operation single external crystal and internal crystal oscillator Ethernet Interfaces supported by PFE 211 FC-LGA package, 9.6 mm x 9.6 mm Two quad-speed Ethernet MACs supporting 2.5G, 1G, 100M, 10M Support for RGMII, SGMII, 2.5G SGMII Energy efficient Ethernet support (802.3 az) High-speed peripheral interfaces One PCIe 2.0 controller, supporting x1 operation One Serial ATA (SATA 3.0) controller One USB 3.0/2.0 controller with integrated PHY One USB 2.0 controller with ULPI interface NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products.Table of Contents 1 Overview.............................................................................................. 3 3.17 USB 2.0 ULPI interface............................................................ 61 2 Pin assignments.................................................................................... 3 3.18 USB 3.0 interface...................................................................... 63 2.1 211 LGA ball layout diagrams.................................................. 3 3.19 High-speed serial interfaces (HSSI).......................................... 66 2.2 Pinout list...................................................................................9 3.20 I2C ............................................................................................ 94 3 Electrical characteristics.......................................................................25 3.21 JTAG......................................................................................... 97 3.1 Overall DC electrical characteristics.........................................25 3.22 SPI interface.............................................................................. 99 3.2 Power up sequencing.................................................................30 3.23 QuadSPI interface......................................................................102 3.3 Power-down requirements.........................................................32 4 Hardware design considerations...........................................................106 3.4 Power characteristics.................................................................33 4.1 Clock ranges.............................................................................. 106 3.5 I/O power dissipation ............................................................... 34 5 Thermal characteristics........................................................................ 107 3.6 Power-on ramp rate................................................................... 36 5.1 Recommended thermal model...................................................107 3.7 RESET initialization..................................................................36 5.2 Temperature diode.....................................................................107 3.8 Input clocks............................................................................... 37 5.3 Thermal management information............................................ 108 3.9 DDR3L SDRAM controller...................................................... 38 6 Package information.............................................................................111 3.10 DUART..................................................................................... 43 6.1 Package parameters for the LS1012A device............................111 3.11 Enhanced secure digital host controller (eSDHC).....................44 6.2 Mechanical dimensions of the LS1012A device.......................111 3.12 PFE (Ethernet Interface)............................................................52 7 Security fuse processor.........................................................................116 3.13 EMI1 management.................................................................... 54 8 Ordering information............................................................................116 3.14 GPIO..........................................................................................56 8.1 Part numbering nomenclature....................................................116 3.15 SAI/I2S interface.......................................................................58 8.2 Part marking ............................................................................. 117 3.16 Flextimer interface.....................................................................59 9 Revision history....................................................................................118 QorIQ LS1012A Data Sheet, Rev. 2, 01/2019 2 NXP Semiconductors