Data Sheet: Technical Data Document identifier: LX2160A Rev. 0 07/2020 LX2160A QorIQ LX2160A, LX2120A, LX2080A Data Sheet Arm Cortex -A72 cores: Ethernet interfaces supporting IEEE 1588 Up to 2.2 GHz Up to 18 Ethernet MACs Single-threaded cores with 48KB L1 instruction Support for 10G-SXGMII (USXGMII) cache and 32KB L1 data cache Support for SGMII (and 1000Base-KX) LX2160A has 16 cores, 8 MB L2 cache LX2120A Support for XFI, SFI, and 10GBase-KR has 12 cores, 6 MB L2 cache LX2080A has 8 Support for CAUI4 (100G), CAUI2 (50G), 25G-AUI cores, 8 MB L2 cache (25G) Cache Coherent Interconnect Fabric Support for XLAUI4 (and 40GBase-KR4) for 40G Up to 1500 MHz Support for two RGMII parallel interfaces 8 MB Level 3 cache with ECC and On-Chip Energy-efficient support (802.3az) Memory (OCM) mode Additional peripheral interfaces Two 72-bit (64-bit + ECC) 3.2 GT/s DDR4 SDRAM memory controllers with ECC Two USB 3.0 controllers with integrated PHY Datapath acceleration architecture 2.0 (DPAA2) Two enhanced secure digital host controllers Packet parsing, classification, and distribution Two Controller Area Network (CAN) modules, (WRIOP) optionally supporting Flexible Datarate Queue and Hardware buffer management Flexible Serial Peripheral Interface (FlexSPI) and three Serial Peripheral Interface (SPI) controllers Cryptography acceleration (SEC) at up to 50 Gbps Eight I2C controllers Decompression/compression acceleration (DCE) at up to 100 Gbps Four UARTs Queue Direct Memory Access (QDMA) engine General Purpose IO (GPIO) Management Complex (MC) Support for hardware virtualization and partitioning enforcement (ARM MMU-500) 2 MB Packet Express Buffer Global interrupt controller (ARM GIC-500) L2 Switching (114 Gbps) QorIQ platform trust architecture 3.0 with 256 KB on-chip 24 SerDes lanes at up to 25 Gbps RAM for trusted accesses High-speed peripheral interfaces Two Flextimers, one secure watchdog timer and one Two PCIe Gen 3.0 8-lane controllers supporting non-secure watchdog timer SR-IOV Debug supporting run control, data acquisition, high- Four PCIe Gen 3.0 4-lane controllers speed trace, and performance/event monitoring Four serial ATA (SATA 3.0) controllers Support for Voltage ID (VID) for yield improvement NXP reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.Contents 1 Introduction.......................................................................... 4 3.3 Power sequencing................................... 92 1.1 Device selection.........................................5 3.4 Power-down requirements....................... 93 3.5 Power-on ramp rate................................. 94 2 Pin assignments.................................................................. 6 3.6 Power characteristics...............................94 2.1 1517 ball layout diagrams.......................... 6 3.7 Input clocks.............................................. 95 2.2 Pinout list................................................. 11 3.7.1 USB reference clock specifications.........95 2.2.1 DDR1 pins...............................................84 3.7.2 Gigabit Ethernet reference clock timing.. 95 2.2.2 DDR2 pins...............................................84 3.7.3 DDR clock (DDRCLK)............................. 95 2.2.3 I2C1 pins................................................. 84 3.7.4 Differential system clock 2.2.4 I2C2 pins................................................. 84 (DIFF SYSCLK P/DIFF SYSCLK N) 2.2.5 I2C3 pins................................................. 84 timing specifications..................................... 96 2.2.6 I2C4 pins................................................. 84 3.7.5 Other input clocks................................... 98 2.2.7 I2C5 pins................................................. 85 3.8 Reset initialization timing specifications...98 2.2.8 I2C6 pins................................................. 85 3.9 Battery-backed security monitor.............. 98 2.2.9 I2C7 pins................................................. 85 3.9.1 Battery-backed security monitor AC 2.2.10 I2C8 pins............................................... 85 timing specifications..................................... 98 2.2.11 XSPI1 pins............................................ 85 3.10 DDR4 SDRAM controller....................... 99 2.2.12 eSDHC1 pins........................................ 85 3.10.1 DDR4 SDRAM controller DC 2.2.13 eSDHC2 pins........................................ 85 electrical characteristics............................... 99 2.2.14 UART pins.............................................85 3.10.2 DDR4 SDRAM controller AC timing 2.2.15 Interrupt controller pins......................... 85 specifications................................................ 99 2.2.16 Trust pins.............................................. 85 3.11 Universal asynchronous receiver/ 2.2.17 System control pins...............................85 transmitter (UART)....................................103 2.2.18 Clocking pins.........................................85 3.11.1 UART DC electrical characteristics..... 103 2.2.19 Debug pins............................................ 85 3.11.2 UART AC timing specifications........... 103 2.2.20 DFT pins................................................85 3.12 Enhanced secure digital host controller 2.2.21 JTAG pins............................................. 86 (eSDHC)................................................... 104 2.2.22 Analog pins........................................... 86 3.12.1 eSDHC DC electrical characteristics...104 2.2.23 SerDes1 pins.........................................86 3.12.2 eSDHC AC timing specifications.........104 2.2.24 SerDes2 pins.........................................86 3.13 Ethernet interface (EMI, RGMII, and 2.2.25 SerDes3 pins.........................................86 IEEE Std 1588 ).......................................115 2.2.26 USB PHY pins.......................................86 3.13.1 Ethernet management interface (EMI) 115 2.2.27 EC1 pins................................................86 3.13.2 Reduced media-independent 2.2.28 EC2 pins................................................86 interface (RGMII)........................................ 117 2.2.29 GPIO pins..............................................86 3.13.3 IEEE 1588...........................................119 2.2.30 FlexTimer pins.......................................86 3.14 General purpose input/output (GPIO).. 121 2.2.31 CAN pins............................................... 86 3.14.1 GPIO DC electrical characteristics......121 2.2.32 Power-on-reset configuration pins........ 86 3.14.2 GPIO AC timing specifications............ 122 2.2.33 SPI1 pins...............................................86 3.15 Flextimer interface............................... 122 2.2.34 SPI2 pins...............................................86 3.15.1 Flextimer DC electrical characteristics 122 2.2.35 SPI3 pins...............................................87 3.15.2 Flextimer AC timing specifications...... 123 2.2.36 IEEE 1588 pins..................................... 87 3.16 Generic interrupt controller (GIC).........123 2.2.37 Power and ground pins......................... 87 3.16.1 GIC DC electrical characteristics........ 123 2.2.38 No connect pins.................................... 87 3.16.2 GIC AC timing specifications...............124 3 Electrical characteristics.................................................... 87 3.17 I2C....................................................... 124 3.1 Overall DC electrical characteristics........ 87 3.17.1 I2C DC electrical characteristics......... 124 3.1.1 Absolute maximum ratings......................87 3.17.2 I2C AC timing specifications............... 125 3.1.2 Recommended Operating Conditions..... 89 3.18 JTAG....................................................127 3.1.3 Output drive capabilities..........................91 3.18.1 JTAG DC electrical characteristics......127 3.2 General AC timing....................................92 3.18.2 JTAG AC timing specifications............127