Layerscape LX2162A Communications Processor The Layerscape LX2162A processor features 16 Arm v8 Cortex -A72 cores for server- level performance in a tiny 23 x 23 mm package. With twelve SerDes lanes supporting PCIe Gen 3 and 4 x 25 Gigabit Ethernet and the low power of 16nm FinFET process technology, this processor is ideal for space-constrained high-performance boards. 2 MB packet caching buffer OVERVIEW The LX2162A processor squeezes the processing 12 SerDes lanes, operating up to 25 GHz capability of the popular LX2160A device into a package Up to 12 Ethernet ports that is nearly one quarter the size, making it suitable Supported Ethernet speeds include 1, 2.5, 10, 25, 40, for small boards such as network interface cards, COM and 50 Gbit/s Express Type 7 modules, OCP3 mezzanine cards, and custom daughter cards. It retains LX2160As 16 105 Gbit/s Layer 2 Ethernet switch Cortex-A72 cores, 50 Gbit/s security engine and 88 Gbit/s Up to 12 PCIe Gen3 lanes, supporting three ports, as data compression engine. It has 12 SerDes lanes at up wide as x8 to 25 Gbit/s, which can support four 25 Gbit Ethernet 50 Gbit/s security accelerator and x8 PCIe Gen3 simultaneously, among many other combinations. 88 Gbit/s data compression/decompression engine 4 x SATA3.0 FEATURES Secure boot and Arm TrustZone technology 16 64-bit Armv8 Cortex-A72 CPU cores, running up to 2.0 GHz 2 x SD / eMMC, 3 x SPI, one 8-bit SPI, 2 x DUART, 2 8 x I C, 1 x USB3.0, 2 x CAN (FD optional) 16 MB cache DDR4 72b including ECC, to 2900 MT/s, maximum capacity of 32 GBTARGET APPLICATIONS APPLICATION EXAMPLES RELEVANT FEATURES The LX2162A processor targets 8 x PCIe Gen 3 with SR-IOV space-constrained boards. Designers 2 x 25 Gbit/s NIC Low power due to 16nm FinFET process Data center technology Control plane on FPGA-based can use it on a network interface offload NIC Data-center friendly 25 Gbit Ethernet card (NIC) as the control lane to ports a data path ASIC or FPGA. It also can be the main processor on COM Express Type 7 23 x 23 mm package a 2 x 25 Gbit Ethernet NIC. For Standard industrial Mini-ITX Three PCIe Gen3 controllers module industrial applications, designers can OCP 3.0 mezzanine card Flexible SerDes configs incorporate it into standard module form factors such as COM Express, LAYERSCAPE LX2162A BLOCK DIAGRAM mini-ITX and OCP 3.0. LAYERSCAPE LX2162A BLOCK DIAGRAM Arm A72 A72 A72 A72 A72 A72 A72 Cortex -A72 A72 A72 A72 A72 A72 A72 A72 A72 72-bit DDR4 with 1MB L2 1MB L2 1MB L2 1MB L2 1MB L2 1MB L2 1MB L2 1MB L2 ECC Interconnect 8 MB Platform Cache I/O MMU I/O MMU I/O MMU I/O MMU Secure Boot 2 MB Packet Express Buffer RELATED SOFTWARE Arm TrustZone Power Management WRIOP Linux SDK for Layerscape SEC 50 G SD/eMMC Processors 105 Gbit/s 2 x DUART 1/2.5/10/25/40/50 Gbit Ethernet 2 DCE 88 G 8 x I C CodeWarrior Development SPI, GPIO, JTAG Software for Armv8 64-bit based USB3.0 + PHY QB-Man 12 lanes up to 25 GHz Layerscape Series Processors 2 x CAN FD LAYERSCAPE LX2162A FAMILY MEMBERS LX2162A LX2122A LX2082A Cores 16 12 8 L2 Cache 8 MB 6 MB 8 MB SerDes 12 lanes at up to 25 GHz PCIe 3 x Gen3, max width of x8 DDR DDR4, 2900 MT/s, 32 GB capacity Platform cache + PEB 10 MB 105 Gbit/s L2 switch, supporting combinations of 12 ports of Ethernet 1, 2.5, 10, 25, 40, and 50 Gbit Ethernet Security 50 Gbit/s Data Compression Engine 88 Gbit/s Package 23 x 23 mm, 1150 pins www.nxp.com/LX2162A NXP, the NXP logo, CodeWarrior and Layerscape are trademarks of NXP B.V. All other product or service names are the property of their respective owners. Arm, Cortex and TrustZone are trademarks or registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere. The related technology may be protected by any or all patents, copyrights, designs and trade secrets. All rights reserved. 2020 NXP B.V. Document Number: LX2162AFSA4 REV 3 Date of Release: October 2020 x8 Gen3 PCIe x4 Gen3 PCIe x4 Gen3 PCIe SATA3 SATA3 SATA3 SATA3