MC13850-2400EVK NXP

Document Number: MC13850 Freescale Semiconductor Rev. 1, 12/2010 Data Sheet: Advance Information MC13850 Package Information Plastic Package: MLPD-8 MC13850 2.0 x 2.0 x 0.6 mm Case: 2128-01 Low Noise Amplifier with Bypass Ordering Information Switch Device Device Marking Package MC13850EP 850 MLPD-8 Contents: 1 Introduction 1 Introduction .1 The MC13850 is a cost-effective, high IP3 LNA with low 2 Electrical Specifications .3 noise figure. This is the leadless package version of the 3 Scattering and Noise Parameters 8 4 Application Information .34 MBC13720 device. As with the MBC13720, this device 5 Printed Circuit Board and Bill of Materials .46 is designed for general purpose RF applications, yet has 6 Packaging 52 excellent high frequency gain and noise figure. An 7 Product Documentation .53 integrated bypass switch is included to preserve high 8 Revision History .53 input intercept performance. The input and output match are external to allow maximum design flexibility. The LNA has two selectable IP3 modes, a bypass mode and a standby mode. The MC13850 is fabricated with an advanced RF BiCMOS process using the SiGe:C module and is packaged in the MLPD-8 leadless package. 1.1 Features RF input frequency: 400 MHz to 2500 MHz Gain: 21 dB at 470 MHz, 14.5 dB at 1960 MHz and 12 dB at 2.4 GHz in high IP3 mode Input third order intercept point (IIP3): 10 dBm at 1960 MHz, 13 dBm at 2.4 GHz, and -2.5 dBm at 860 MHz in high IP3 mode This document contains information on a new product. Specifications and information herein are subject to change without notice. Freescale Semiconductor, Inc., 20062010. All rights reserved. Introduction Noise Figure (NF): 1.6 dB at 860 MHz, 1.4 dB at 1960 MHz, and 1.55 dB at 2400 MHz in low IP3 mode Output 1 dB compression point (P1dB): 9 dBm at 470 MHz and 11.5 dBm at 1060 MHz in high IP3 mode Selectable IP3 mode allows for running at the desired IP3 performance for a receiver s linearity requirements Bypass mode has return losses comparable to active mode, for use in systems with filters and duplexers Bypass mode improves dynamic range in variable signal strength environments Integrated logic-controlled standby mode with current drain < 1A Total supply current: 5 mA at 2.7 V in low IP3 mode and 10 mA in high IP3 mode. Bypass mode <10 A In a receiver system with 20% active mode and 80% bypass mode, the average current drain is 1mA On-chip bias sets the bias point Bias stabilized for device and temperature variations MLPD-8 leadless package with low parasitics 470-860, 900, 1960, and 2400 MHz application circuit evaluation boards with characterization data are available Available in tape and reel packaging Figure 1 shows a simplified block diagram of the MC13850 with the pinouts and location of the Pin 1 designator on the package. Gnd Enable2 Enable1 Vcc 8 7 6 5 Gain Logic Enable Pin 1 Designator on Package 3 1 2 4 NC RF OUT RF IN Gnd . Figure 1. Simplified Block Diagram MC13850 Advance Information, Rev. 1 2 Freescale Semiconductor