MC33661PEFR2 NXP

Document Number: MC33661 Freescale Semiconductor Rev. 8.0, 4/2013 Technical Data Local Interconnect Network (LIN) Enhanced Physical 33661 Interface with Selectable Slew- Rate LIN PHYSICAL INTERFACE Local interconnect network (LIN) is a serial communication protocol designed to support automotive networks in conjunction with controller area network (CAN). As the lowest level of a hierarchical network, LIN enables cost-effective communication with sensors and actuators when all the features of CAN are not required. This device is powered by SMARTMOS technology. The 33661 is a physical layer component dedicated to automotive LIN sub-bus applications. It offers slew-rate selection for optimized operation at 10 kbps and 20 kbps, fast baud rate (above 100 kbps) for test and programming modes, excellent radiated emission performance, and safe behavior in the event of LIN bus short-to-ground or LIN bus leakage during low power mode. EF SUFFIX (PB-FREE) 98ASB42564B The 33661 is compatible with LIN Protocol Specification 2.0. 8-PIN SOICN Features Operational from V 6.0 V to 18 V DC, functional up to 27 V DC, SUP and handles 40 V during load dump ORDERING INFORMATION Active bus waveshaping offering excellent radiated emission performance Device (For Tape and Temperature 5.0 kV ESD on LIN bus pin Package Reel, add an R2 Range (T ) A 30 k internal pull-up resistor Suffix) LIN bus short-to-ground or high leakage in Sleep mode -18 V to +40 V DC voltage at LIN pin MC33661PEF - 40 to 125C 8 SOICN 8.0 A in Sleep mode Local and remote wake-up capability reported by INH and RXD pins 5.0 V and 3.3 V compatible digital inputs without any external components required V PWR 33661 WAKE VSUP INH V DD EN Regulator 12 V MCU LIN Bus RXD 5.0 V LIN TXD GND Figure 1. 33661 Simplified Application Diagram Freescale Semiconductor, Inc. reserves the right to change the detail specifications, as may be required, to permit improvements in the design of its products. Freescale Semiconductor, Inc., 2006 - 2013. All rights reserved.INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM VSUP WAKE 20 A INH Control EN INH Control RXD 30 k Receiver LIN TXD Slope GND Control Figure 2. 33661 Simplified Internal Block Diagram 33661 Analog Integrated Circuit Device Data 2 Freescale Semiconductor