NXP Semiconductors Document Number: MC33889 Rev. 15.0, 8/2016 Technical Data System basis chip (SBC) with low 33889 speed fault tolerant CAN interface The 33889 is an SBC having a fully protected, fixed 5.0 V low drop-out regulator, with current limit, overtemperature prewarning and reset. An SBC device is a monolithic IC combining many functions repeatedly found in SYSTEM BASIS CHIP standard microcontroller-based systems, e.g., protection, diagnostics, communication, power, etc. An output drive with sense input is also provided to implement a second 5.0 V regulator using an external PNP. The 33889 has Normal, Standby, Stop and Sleep modes an internally switched high-side power supply output with two wake-up inputs programmable timeout or window watchdog, Interrupt, Reset, serial peripheral interface (SPI) input control, and a low-speed fault tolerant CAN transceiver, compatible with CAN 2.0 A and B protocols for module-to- module communications. The combination is an economical solution for power management, high-speed communication, and control in MCU-based systems. EG SUFFIX (PB-FREE) This device is powered by SMARTMOS technology. PLASTIC PACKAGE 98ASB42345B Features 28-PIN SOICW VDD1: 5.0 V low drop voltage regulator, current limitation, overtemperature detection, monitoring and reset function with total current capability 200 mA V2: tracking function of VDD1 regulator control circuitry for external bipolar ORDERING INFORMATION ballast transistor for high flexibility in choice of peripheral voltage and current Device supply Temperature (Add R2 Suffix for Package Range (T ) Four operational modes A Tape and Reel) Low standby current consumption in Stop and Sleep modes MC33889BPEG Built-in low speed 125 kbps fault tolerant CAN physical interface. -40 to 125 C 28 SOICW *MC33889DPEG External high voltage wake-up input, associated with HS1 V switch BAT 150 mA output current capability for HS1 V switch allowing drive of *Recommended for new designs BAT external switches pull-up resistors or relays V PWR 33889 VDD1 VSUP 5.0 V V 2 GND V2CTRL RST V2 MCU INT HS1 Local Module Supply CS CS L0 Wake-Up Inputs SCLK SCLK L1 SPI MOSI MOSI WDOG Safe Circuits MISO MISO RTH Twisted TXD CANH CAN Bus RXD CANL Pair RTL Figure 1. 33889 simplified application diagram 2016 NXP B.V.1 Device variations (1) Table 1. Device variations between the 33889D and 33889B versions Device part number Parameters Symbol Trait (2) (2) MC33889B MC33889D Min. 3.2 V 3.5 V Differential Receiver, Recessive To Dominant Threshold (By Typ 2.6 V 3.0 V Definition, V = V -V ) V DIFF CANH CANL DIFF1 Max. 2.1 V 2.5 V Min. 3.2 V 3.5 V Differential Receiver, Dominant To Recessive Threshold (Bus Typ 2.6 V 3.0 V Failures 1, 2, 5) V DIFF2 Max. 2.1 V 2.5 V Min. 50 mA 50 mA CANH Output Current (V = 0 TX = 0.0) Typ 75 mA 100 mA CANH I CANH Max. 110 mA 130 mA Min. 50 mA 50 mA CANL Output Current (V = 14 V TX = 0.0) Typ 90 mA 140 mA CANL I CANL Max. 135 mA 170 mA Detection threshold for Short circuit to Battery voltage Vcanh Max. Vsup/2 + 5V Vsup/2 + 4.55V loop time Tx to Rx, no bus failure, ISO configuration tLOOPRD Max. N/A 1.5us loop time Tx to Rx, with bus failure, ISO configuration tLOOPRD-F Max. N/A 1.9us loop time Tx to Rx, with bus failure and +-1.5V gnd shift, tLOOPRD/DR-F+GS N/A 3.6us 5 node network, ISO configuration Min. N/A 8 Minimum Dominant time for Wake up on CANL or CANH (Tem tWAKE typ 30 16 Vbat mode) Max. N/A 30 not specified, 25us spec T2SPI timing T2spi Min. 25us applied Device behavior after 4 non consecutive CANH or CANL open wire recovery principle Reference MC33889B on page 32 after 4 consecutive pulses pulses Rx recessive, dominant Rx behavior in TermVbat mode Reference MC333889D on page 32 Rx recessive, no pulse pulse to signal bus traffic Notes 1. This datasheet uses the term 33889 in the inclusive sense, referring to both the D version (33889D) and the B version (33689B). 2. The 33889D and 33889B versions are nearly identical. However, where variations in characteristic occur, these items will be separated onto individual lines. 33889 2 NXP Semiconductors