Document Number: MC33989 Freescale Semiconductor Rev. 15.0, 6/2013 Technical Data System Basis Chip with 33989 High Speed CAN Transceiver The 33989 is a monolithic integrated circuit combining many functions used by microcontrollers (MCU) found in automotive Engine Control Units (ECUs). The device incorporates functions such as: two SYSTEM BASIS CHIP voltage regulators, four high-voltage (wake-up) inputs, a 1.0 Mbaud WITH HIGH SPEED CAN capable CAN physical interface, an SPI interface to the MCU and VSUP monitoring and fault detection circuitry. The 33989 also provides reset control in conjunction with VSUP monitoring and the watchdog timer features. Also, an Interrupt can be generated, for the MCU, based on CAN bus activity as well as mode changes. Features V : Low drop voltage regulator, current limitation, DD1 overtemperature detection, monitoring, and reset function V : Total current capability 200 mA DD1 V2: Tracking function of V regulator. Control circuitry for external DD1 EG SUFFIX (PB-FREE) bipolar ballast transistor for high flexibility in choice of peripheral 98ASB42345B voltage and current supply 28-PIN SOICW Low stand-by current consumption in Stop and Sleep modes High speed 1.0 MBaud CAN physical interface Four external high voltage wake-up inputs associated with HS1 ORDERING INFORMATION V switch BAT 150 mA output current capability for HS1 V switch allowing drive BAT Temperature Device Package of external switches pull-up resistors or relays Range (T ) A V failure detection SUP MC33989PEG/R2 - 40 to 125 C 28 SOICW 40 V maximum transient voltage V PWR 33989 VDD1 VSUP 5.0 V V2 GND MCU V2CTRL RST V2 INT HS1 Local Module Supply CS L0 CS SCLK SCLK L1 SPI Wake-Up Inputs MOSI MOSI L2 MISO MISO L3 WD Safe Circuits CANH Twisted TX CAN Bus RX Pair CANL Figure 1. MC33989 Simplified Application Diagram *This document contains certain information on a product under development. Freescale reserves the right to change or discontinue this product without notice. Freescale Semiconductor, Inc., 2007 - 2013. All rights reserved.INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM V2CTRL VSUP Monitor Dual Voltage Regulator VSUP V2 VDD1 Monitor VDD1 HS1 Control Oscillator INT HS1 Interrupt Watchdog WD L0 Reset Programmable RST Wake-Up Inputs L1 Mode Control L2 CS L3 SCLK TX SPI Interface High Speed MOSI RX 1.0 MB/s CAN Physical MISO CAN H V Interface 2 GND CAN L Figure 2. 33989 Simplified Internal Block Diagram 33989 Analog Integrated Circuit Device Data 2 Freescale Semiconductor