Document Number: MPC7448EC Freescale Semiconductor Rev. 4, 3/2007 Technical Data MPC7448 RISC Microprocessor Hardware Specifications Contents This document is primarily concerned with the MPC7448, 1. Overview . 1 which is targeted at networking and computing systems 2. Features 3 applications. This document describes pertinent electrical and 3. Comparison with the MPC7447A, MPC7447, MPC7445, and MPC7441 7 physical characteristics of the MPC7448. For information 4. General Parameters . 9 regarding specific MPC7448 part numbers covered by this 5. Electrical and Thermal Characteristics 9 document and part numbers covered by other documents, refer 6. Pin Assignments 24 to Section 11, Part Numbering and Marking. For functional 7. Pinout Listings . 25 8. Package Description . 29 characteristics of the processor, refer to the MPC7450 RISC 9. System Design Information . 35 Microprocessor Family Reference Manual. 10. Document Revision History . 55 To locate any published updates for this document, refer to the 11. Part Numbering and Marking 57 website listed on the back cover of this document. 1Overview The MPC7448 is the sixth implementation of fourth- generation (G4) microprocessors from Freescale. The MPC7448, built on Power Architecture technology, implements the PowerPC instruction set architecture version 1.0 and is targeted at networking and computing systems applications. The MPC7448 consists of a processor core and a 1-Mbyte L2. Figure 1 shows a block diagram of the MPC7448. The core is a high-performance superscalar design supporting a double-precision floating-point unit and a SIMD multimedia unit. The memory storage subsystem supports the MPX bus protocol and a subset of the 60x bus protocol to main memory and other system resources. Freescale Semiconductor, Inc., 2005, 2007. All rights reserved.Overview Figure 1. MPC7448 Block Diagram MPC7448 RISC Microprocessor Hardware Specifications, Rev. 4 2 Freescale Semiconductor Additional Features 128-Bit (4 Instructions) Instruction Unit Instruction MMU Instruction Queue Time Base Counter/Decrementer (12-Word) Clock Multiplier 128-Entry SRs Branch Processing Unit Fetcher (Shadow) JTAG/COP Interface ITLB 32-Kbyte Tags Thermal/Power Management BTIC (128-Entry) CTR I Cache Performance Monitor IBAT Array BHT (2048-Entry) LR Out-of-Order Issue of AltiVec Instr. Dispatch Unit Data MMU 32-Kbyte Completion Unit Tags 96-Bit (3 Instructions) 128-Entry D Cache SRs Completion Queue (Original) DTLB (16-Entry) VR Issue GPR Issue FPR Issue DBAT Array (4-Entry/2-Issue) (6-Entry/3-Issue) (2-Entry/1-Issue) Reservation Stations (2-Entry) EA Completes up Vector to three Load/Store Unit Touch instructions PA Queue Vector Touch Engine per clock Reservation Reservation Reservation Reservation Reservation Stations (2) Station Stations (2) Station Station + VR File GPR File (EA Calculation) FPR File Finished L1 Castout 16 Rename 16 Rename 16 Rename Stores Buffers Buffers Buffers Reservation Reservation Integer Integer Floating- Reservation Reservation Integer Integer Unit 2 Unit 1 Station Point Unit Station Station Station Unit 2 Unit 2 (3) L1 Push + x + x + + Vector Vector Vector Completed FPSCR FPSCR Vector Permute Integer Integer Stores Load Mi ss FPU 32-Bit 64-Bit 64-Bit 32-Bit 32-Bit Unit Unit 2 Unit 1 128-Bit 128-Bit Memory Subsystem L1 Store Queue 1-Mbyte Unified L2 Cache Controller System Bus Interface (LSQ) L1 Service Line Load Block 0 (32-Byte) Block 1 (32-Byte) Queues Bus Store Queue Queue (11) Tags Status Status L1 Load Queue (LLQ) Castout Queue (5) / L1 Load Miss (5) Push L2 Store Queue (L2SQ) 1 Queue (6) Snoop Push/ L1 Castouts L2 Prefetch (3) Interventions (4) Instruction Fetch (2) Bus Accumulator Cacheable Store Miss (2) 64-Bit 36-Bit Notes: The Castout Queue and Push Queu e share resources such for a combined total of 6 entries. Address Bus Data Bus The Castout Queue itself is limited to 5 entries, ensuring 1 entry will be available for a push.