MPC7457EC Freescale Semiconductor Rev. 8, 04/2013 Data Sheet: Technical Data MPC7457 RISC Microprocessor Contents This hardware specification is primarily concerned 1. Overview . 2 with the MPC7457 however, unless otherwise 2. Features 2 noted, all information here also applies to the 3. Comparison with the MPC7455, MPC7445, MPC7450, MPC7451, and MPC7441 9 MPC7447. The MPC7457 and MPC7447 are 4. General Parameters 11 implementations of the PowerPC microprocessor 5. Electrical and Thermal Characteristics . 11 family of reduced instruction set computer (RISC) 6. Pin Assignments 36 microprocessors. This hardware specification 7. Pinout Listings . 38 8. Package Description . 44 describes pertinent electrical and physical 9. System Design Information . 50 characteristics of the MPC7457. For functional 11. Document Revision History . 68 characteristics of the processor, refer to the 10. Part Numbering and Marking 65 MPC7450 RISC Microprocessor Family Users Manual. To locate any published updates for this hardware specification, refer to the website listed on the back page of this document. Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. 2006 Freescale Semiconductor, Inc. All rights reserved.Overview 1 Overview The MPC7457 is the fourth implementation of the fourth generation (G4) microprocessors from Freescale. The MPC7457 implements the full PowerPC 32-bit architecture and is targeted at networking and computing systems applications. The MPC7457 consists of a processor core, a 512-Kbyte L2, and an internal L3 tag and controller that support a glueless backside L3 cache through a dedicated high-bandwidth interface. The MPC7447 is identical to the MPC7457 except that it does not support the L3 cache interface. Figure 1 shows a block diagram of the MPC7457. The core is a high-performance superscalar design supporting a double-precision floating-point unit and a SIMD multimedia unit. The memory storage subsystem supports the MPX bus protocol and a subset of the 60x bus protocol to main memory and other system resources. The L3 interface supports 1, 2, or 4 Mbytes of external SRAM for L3 cache and/or private memory data. For systems implementing 4 Mbytes of SRAM, a maximum of 2 Mbytes may be used as cache the remaining 2 Mbytes must be private memory. Note that the MPC7457 is a footprint-compatible, drop-in replacement in a MPC7455 application if the core power supply is 1.3 V. 2Features This section summarizes features of the MPC7457 implementation of the PowerPC architecture. Major features of the MPC7457 are as follows: High-performance, superscalar microprocessor As many as four instructions can be fetched from the instruction cache at a time. As many as three instructions can be dispatched to the issue queues at a time. As many as 12 instructions can be in the instruction queue (IQ). As many as 16 instructions can be at some stage of execution simultaneously. Single-cycle execution for most instructions One instruction per clock cycle throughput for most instructions Seven-stage pipeline control Eleven independent execution units and three register files Branch processing unit (BPU) features static and dynamic branch prediction 128-entry (32-set, four-way set associative) branch target instruction cache (BTIC), a cache of branch instructions that have been encountered in branch/loop code sequences. If a target instruction is in the BTIC, it is fetched into the instruction queue a cycle sooner than it can be made available from the instruction cache. Typically, a fetch that hits the BTIC provides the first four instructions in the target stream. 2048-entry branch history (BHT) with 2 bits per entry for 4 levels of predictionnot-taken, strongly not-taken, taken, and strongly taken Up to three outstanding speculative branches MPC7457 RISC Microprocessor Hardware Specifications, Rev. 8 2 Freescale Semiconductor