Freescale Semiconductor Document Number: MPC8610EC Rev. 2, 01/2009 Data Sheet MPC8610 Integrated Host Processor Hardware Specifications Features Boot sequencer Optionally loads configuration data from serial ROM at High-performance, 32-bit e600 core, that implements the 2 reset via I C interface Power Architecture technology Can be used to initialize configuration registers and/or Eleven execution units and three register files memory Two separate 32-Kbyte instruction and data level 1 (L1) 2 Supports extended I C addressing mode caches DUART Integrated 256-Kbyte, eight-way set-associative unified Fast InfraRed interface instruction and data level 2 (L2) cache with ECC Serial peripheral interface 36-bit real addressing Master or slave support Multiprocessing support features Dual integrated four-channel DMA controllers Power and thermal management All channels accessible by both local and remote masters MPX coherency module (MCM) Supports transfers to or from any local memory or I/O Address translation and mapping units (ATMUs) port DDR/DDR2 memory controller Ability to start and flow control each DMA channel 64- or 32-bit data path (72-bit with ECC) from external 3-pin interface Up to 533-MHz DDR2 data rate and up to 400 MHz Watchdog timer DDR data rate Dual global timer modules Up to 16 Gbytes memory 32-bit PCI interface, 33 or 66 MHz bus frequency Enhanced local bus controller (eLBC) Dual PCI Express controllers Operating at up to 133 MHz PCI Express 1.0a compatible Eight chip selects PCI Express controller 1 supports x1, x2, and x4 link Display interface unit widths PCI Express controller 2 supports x1, x2, x4, and Maximum display resolution: 12801024 x8 link widths Maximum display refresh rate: 60 Hz 2.5 Gbaud, 2.0 Gbps lane Display color depth: up to 24 bpp Device performance monitor Display interface: parallel TTL Supports eight 32-bit counters that count the occurrence OpenPIC-compliant programmable interrupt controller of selected events (PIC) Ability to count up to 512 counter-specific events Supports 16 programmable interrupt and processor task Supports 64 reference events that can be counted on any priority levels of the 8 counters Supports 12 discrete external interrupts and 48 internal Supports duration and quantity threshold counting interrupts Burstiness feature that permits counting of burst events Eight global high resolution timers/counters that can with a programmable time between bursts generate interrupts Triggering and chaining capability Support for PCI Express message-shared interrupts Ability to generate an interrupt on overflow (MSIs) 2 IEEE Std 1149.1 compliant, JTAG boundary scan Dual I C controllers 2 Available as 783-pin, flip-chip, plastic ball grid array Master or slave I C mode support (FC-PBGA) Freescale Semiconductor, Inc., 2008, 2009. All rights reserved.Table of Contents 1 Pin Assignments and Reset States .4 3.1 System Clocking . 72 2 Electrical Characteristics 15 3.2 Power Supply Design and Sequencing 76 2.1 Overall DC Electrical Characteristics 15 3.3 Decoupling Recommendations 77 2.2 Power Sequencing 19 3.4 SerDes Block Power Supply Decoupling 2.3 Power Characteristics 21 Recommendations 77 2.4 Input Clocks .22 3.5 Connection Recommendations 77 2.5 RESET Initialization .25 3.6 Pull-Up and Pull-Down Resistor Requirements 78 2.6 DDR and DDR2 SDRAM .25 3.7 Output Buffer DC Impedance . 78 2.7 Local Bus .31 3.8 Configuration Pin Muxing 79 2.8 Display Interface Unit 36 3.9 JTAG Configuration Signals . 80 2 2.9 I C .39 3.10 Guidelines for High-Speed Interface Termination 83 2.10 DUART .42 3.11 Guidelines for PCI Interface Termination . 84 2.11 Fast/Serial Infrared Interfaces (FIRI/SIRI) .42 3.12 Thermal 84 2.12 Synchronous Serial Interface (SSI) 42 4 Ordering Information . 90 2.13 Global Timer Module .48 4.1 Part Numbers Fully Addressed by This Document . 90 2.14 GPIO .49 4.2 Part Marking 92 2.15 Serial Peripheral Interface (SPI) 50 5 Package Information . 92 2.16 PCI Interface .52 5.1 Package Parameters for the MPC8610 92 2.17 High-Speed Serial Interfaces (HSSI) 54 5.2 Mechanical Dimensions of the MPC8610 FC-PBGA 93 2.18 PCI Express .62 6 Product Documentation . 94 2.19 JTAG .69 7 Revision History 94 3 Hardware Design Considerations 72 MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2 2 Freescale Semiconductor