Document Number: MC94MX21 Freescale Semiconductor Rev. 1.4, 08/2006 Data Sheet: Technical Data MC94MX21 Package Information (MAPBGA289) MC94MX21 Ordering Information: See Table 1 on page 3 333 and 350 MHz Contents 1 Introduction 1 Introduction 1 Freescales i.MX family of microprocessors has 2 Signal Descriptions 5 demonstrated leadership in the portable handheld 3 Specifications 14 4 Pin Assignment and Package Information 95 market. Building on the success of the MX (Media 5 Document Revision History 97 Extensions) series, the i.MX21 (MC94MX21) provides a leap in performance with an ARM926EJ-S microprocessor core that provides accelerated Java support in addition to highly integrated system functions. The i.MX21 device specifically addresses the needs of the smartphone and portable product markets with intelligent integrated peripherals, advanced processor core, and power management capabilities. Thei.MX21 features the advanced and power-efficient ARM926EJ-S core operating at speeds up to 350 MHz and is part of a growing family of Smart Speed products that offer high performance processing optimized for lowest power consumption. On-chip modules such as a video accelerator module, LCD controller, USB On-The- Go, 1-Wire interface, CMOS sensor interface, and synchronous serial interfaces offer designers a rich suite of peripherals that can enhance many products seeking to provide a rich multimedia experience. This document contains information on a new product. Specifications and information herein are subject to change without notice. Freescale Semiconductor, Inc., 2005, 2006. All rights reserved. / Introduction For cost sensitive applications, the NAND Flash controller allows the use of low-cost NAND Flash devices to be used as primary or secondary non-volatile storage. The on-chip error correction code (ECC) and parity checking circuitry of the NAND Flash controller frees the CPU for other tasks. WLAN, Bluetooth and expansion options are provided through PCMCIA/CF, USB, and MMC/SD host controllers. The device is packaged in a 289-pin MAPBGA. System Control Connectivity i.MX21 JTAG/MultiICE CSPI x 3 SSI x 2 System Boot 2 I C Clock Management Audio Mux ARM9 Platform UART x 4 1-WIRE Standard System I/O ARM926EJ-S MAX IrDA Timers x 3 MMU I Cache USB OTG/ 2 Hosts PWM D Cache Bus Control WDOG Memory Expansion Internal Control Memory Control RTC MMC/SD x 2 GPIO PCMCIA/CF DMAC Enhanced Multimedia Accelerator Memory Interface Human Interface (eMMA) CSI SDRAMC Pre- and Post- Processing LCD Controller EIM/BMI SLCD Controller Video Accelerator Keypad NFC Figure 1. i.MX21 Functional Block Diagram 1.1 Conventions This document uses the following conventions: OVERBAR is used to indicate a signal that is active when pulled low: for example, RESET. Logic level one is a voltage that corresponds to Boolean true (1) state. Logic level zero is a voltage that corresponds to Boolean false (0) state. To set a bit or bits means to establish logic level one. To clear a bit or bits means to establish logic level zero. A signal is an electronic construct whose state conveys or changes in state convey information. MC94MX21 Technical Data, Rev. 1.4 2 Freescale Semiconductor