MC9328MX21CJMR2 NXP

Document Number: MC9328MX21 Freescale Semiconductor Rev. 3.4, 07/2010 Data Sheet: Technical Data MC9328MX21 Package Information (MAPBGA289) MC9328MX21 Ordering Information: See Table 1 on page 3 266 MHz Contents 1 Introduction 1. Introduction . 1 2. Signal Descriptions . 5 Freescales i.MX family of microprocessors has 3. Specifications . 14 demonstrated leadership in the portable handheld 4. Pin Assignment and Package Information . 96 5. Document Revision History 99 market. Building on the success of the MX (Media Extensions) series, the i.MX21 (MC9328MX21) provides a leap in performance with an ARM926EJ-S microprocessor core that provides accelerated Java support in addition to highly integrated system functions. The i.MX21 device specifically addresses the needs of the smartphone and portable product markets with intelligent integrated peripherals, advanced processor core, and power management capabilities. The i.MX21 features the advanced and power-efficient ARM926EJ-S core operating at speeds up to 266 MHz and is part of a growing family of Smart Speed products that offer high performance processing optimized for lowest power consumption. On-chip modules such as a video accelerator module, LCD controller, USB On-The- Go, 1-Wire interface, CMOS sensor interface, and synchronous serial interfaces offer designers a rich suite of peripherals that can enhance many products seeking to provide a rich multimedia experience. Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Freescale Semiconductor, Inc., 20052008. All rights reserved.Introduction For cost sensitive applications, the NAND Flash controller allows the use of low-cost NAND Flash devices to be used as primary or secondary non-volatile storage. The on-chip error correction code (ECC) and parity checking circuitry of the NAND Flash controller frees the CPU for other tasks. WLAN, Bluetooth and expansion options are provided through PCMCIA/CF, USB, and MMC/SD host controllers. The device is packaged in a 289-pin MAPBGA. Connectivity System Control i.MX21 JTAG/Multi- CSPI x 3 SSI x 2 System 2 I C Clock Manage- Audio Mux ARM9 Platform UART x 1-WIRE ARM926EJ- MAX Standard System I/O IrDA Timers x I Cache MM USB OTG/ 2 PWM D Bus Con- WDOG Memory Expansion Internal Con- Memory Con- RT MMC/SD x 2 GPI PCMCIA/ DMAC Enhanced Multimedia Accelerator Memory Interface (eMMA) Human Interface SDRAM CSI C Pre- and Post- Process- LCD Controller EIM/BMI SLCD Control- Video Accelera- NFC Key- Figure 1. i.MX21 Functional Block Diagram 1.1 Conventions This document uses the following conventions: OVERBAR is used to indicate a signal that is active when pulled low: for example, RESET. Logic level one is a voltage that corresponds to Boolean true (1) state. Logic level zero is a voltage that corresponds to Boolean false (0) state. To set a bit or bits means to establish logic level one. To clear a bit or bits means to establish logic level zero. MC9328MX21 Technical Data, Rev. 3.4 2 Freescale Semiconductor