Freescale Semiconductor Document Number: MCF51AG128 Rev. 5, 6/2010 Data Sheet: Technical Data MCF51AG128 80 LQFP 64 LQFP MCF51AG128 ColdFire 14 mm 14 mm 10 mm 10 mm Microcontroller 48 LQFP Covers: MCF51AG128 and 64 QFP 7 mm x 7mm 14 mm 14 mm MCF51AG96 The MCF51AG128 is a member of the ColdFire family of Low-voltage detection with reset or interrupt 32-bit variable-length reduced instruction set (RISC) Separate low voltage warning with selectable trip points microcontroller. This document provides an overview of the Illegal opcode and illegal address detection with reset MCF51AG128 series MCUs, focusing on its highly Flash block protection for each array to prevent integrated and diverse feature set. accidental write/erasure Hardware CRC module to support fast cyclic The MCF51AG128 derivative are low-cost, low-power, and redundancy checks high-performance 32-bit ColdFire V1 microcontroller units Debug Support (MCUs) designed for industrial and appliance applications. It Single-wire back ground debug interface is an ideal upgrade for designs based on the MC9S08AC128 Real-time debug support, with six hardware breakpoints series of 8-bit microcontrollers. (4 PC, 1 address pair and 1 data) that can be configured The MCF51AG128 features the following functional units: into a 1- or 2-level trigger 32-bit Version 1 ColdFire central processor unit (CPU) On-chip trace buffer provides programmable start/stop Up to 50.33 MHz ColdFire CPU from 2.7 V to 5.5 V recording conditions Provide 0.94 Dhrystone 2.1 DMIPS per MHz Support for real-time program (and optional partial data) performance when running from internal RAM (0.76 trace using the debug visibility bus DMIPS per MHz when running from flash) DMA Controller Implements Coldfire Instruction Set Revision C Four independently programmable DMA channels (ISA C) provide the means to directly transfer data between On-chip memory system memory and I/O peripherals Up to 128 KB flash memory read/program/erase over DMA enabled peripherals include IIC, SCI, SPI, FTM, full operating voltage and temperature HSCMP, ADC, RTC, and eGPIO, and the DMA request Up to 16 KB random access memory (RAM) from these peripherals can be configured as DMA Security circuitry to prevent unauthorized access to source or as an iEvent input RAM and flash contents CF1 INTC Power-Saving Modes Support of 44 peripheral I/O interrupt requests and seven Three ultra-low power stop modes and reduced power software (one per level) interrupt requests wait mode Fixed association between interrupt request source, level Peripheral clock enable register can disable clocks to and priority, up to two requests can be remapped to the unused modules, thereby reducing currents highest maskable level and priority System Protection Unique vector number for each interrupt source Advanced independent clocked watchdog (WDOG) Support for service routine interrupt acknowledge with features like, robust refresh mechanism, windowed (software IACK) read cycles for improved system mode, high granulation timeout, fast test of timeout, and performance always forces a reset Ability to mask any individual or all interrupt sources Additional external watchdog monitor (EWM) to help reset external circuits Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Freescale Semiconductor, Inc., 2010. All rights reserved. System Clock Sources Oscillator (XOSC) Loop-control pierce oscillator crystal or ceramic resonator range of 31.25 kHz to 38.4 kHz or 1 MHz to 16 MHz Internal Clock Source (ICS) Frequency-locked-loop (FLL) controlled by internal or external reference trimmable internal reference allows 0.2% resolution and 2% deviation (1% across 0 to 70 C) Peripherals ADC 24 analog inputs with 12 bits resolution output formatted in 12-, 10- or 8-bit right-justified format single or continuous conversion (automatic return to idle after single conversion) interrupt or DMA request when conversion complete operation in low-power modes for lower noise operation asynchronous clock source for lower noise operation selectable asynchronous hardware conversion triggers from RTC, PDB, or iEvent dual samples based on hardware triggers during ping-pong mode on-chip temperature sensor PDB 16-bit of resolution with prescaler seven possible trigger events input positive transition of trigger event signal initiates the counter support continuous trigger or single shot, bypass mode supports two triggered delay outputs or ORed together pulsed output could be used for HSCMP windowing signal iEvent User programmable combinational boolean output using the four selected iEvent input channels for use as interrupt requests, DMA transfer requests, or hardware triggers FTM Two 6-channel flexible timer/PWM modules with DMA request option deadtime insertion is available for each complementary channel pair channels operate as pairs with equal outputs, pairs with complimentary outputs or independent channels (with independent outputs) 16-bit free-running counter the load of the FTM registers which have write buffer can be synchronized write protection for critical registers backwards compatible with TPM TPM 16-bit free-running or modulo up/down count operation two channels, each channel may be input capture, output compare, or edge-aligned PWM one interrupt per channel plus terminal count interrupt 16 12 CRC High speed hardware CRC generator circuit using 16-bit shift register CRC16-CCITT compliancy with x + x 5 + x + 1 polynomial error detection for all single, double, odd, and most multi-bit errors programmable initial seed value HSCMP Two analog comparators with selectable interrupt on rising edge, falling edge, or either edges of comparator output the positive and negative inputs of the comparator are both driven from 4-to-1 muxes programmable voltage reference from two internal DACs support DMA transfer IIC Compatible with IIC bus standard and SMBus version 2 features up to 100 kbps with maximum bus loading multi-master operation software programmable for one of 64 different serial clock frequencies programmable slave address and glitch input filter interrupt driven byte-by-byte data transfer arbitration lost interrupt with automatic mode switching from master to slave calling address identification interrupt bus busy detection broadcast and 10-bit address extension address matching causes wake-up when MCU is in Stop3 mode DMA support SCI Two serial communications interface modules with optional 13-bit break full-duplex, standard non-return-to-zero (NRZ) format double-buffered transmitter and receiver with separate enables 13-bit baud rate selection with /32 fractional divide interrupt-driven or polled operation hardware parity generation and checking programmable 8-bit or 9-bit character length receiver wakeup by idle-line or address-mark address match feature in receiver to reduce address-mark wakeup ISR overhead 1/16 bit-time noise detection DMA transmission for both transmit and receive SPI Two serial peripheral interfaces with full-duplex or single-wire bidirectional option double-buffered transmitter and receiver master or slave mode operation selectable MSB-first or LSB-first shifting 8-bit or 16-bit data modes programmable transmit bit rate receive data buffer hardware match feature DMA transmission for transmit and receive Input/Output Up to 69 GPIOs and one Input-only pin Interrupt or DMA request with selectable polarity on all input pins Programmable glitch filter, hysteresis and configurable pull up/down device on all input pins Configurable slew rate and drive strength on all output pins Independent pin value register to read logic level on digital pin Up to 16 rapid general purpose I/O (RGPIO) pins connected to the processors local 32-bit platform bus with set, clear, and faster toggle functionality MCF51AG128 ColdFire Microcontroller, Rev. 5 2 Freescale Semiconductor