Freescale Semiconductor Document NumberDocument Number: MCF51MM256: MCF51MM256 ReRevv.. 5, 07/2012 5, 07/2012 Data Sheet: Technical Data An Energy-Efficient Solution from Freescale MCF51MM256/128 The MCF51MM256 series devices are members of the low-cost, low-power, high-performance ColdFire V1 family of 32-bit microcontrollers (MCUs) designed for handheld metering 80-LQFP 100-LQFP 81-BGA 104-BGA 12mm x 12mm 14mm x 14mm 10mm x 10mm 10mm x 10mm devices. Not all features are available in all devices or packages see Table 1 for a comparison of features by device. 2.0. Allows control, bulk, interrupt and isochronous transfers. 32-Bit ColdFire V1 Central Processor Unit (CPU) SCIx Two serial communications interfaces with optional 13-bit Up to 50.33 MHz ColdFire CPU above 2.4 V and 40 MHz CPU break option to connect Rx input to PRACMP output on SCI1 and above 2.1V and 20 MHz CPU above 1.8 V across temperature SCI2 High current drive on Tx on SCI1 and SCI2 wake-up from range of -40C to 105C. stop3 on Rx edge. ColdFire Instruction Set Revision C (ISA C). SPI1 Serial peripheral interface with 32-bit FIFO buffer 16-bit or 32-bit multiply and accumulate (MAC) supports signed or 8-bit data transfers full-duplex or single-wire bidirectional unsigned integer or signed fractional inputs. double-buffered transmit and receive master or slave mode On-Chip Memory MSB-first or LSB-first shifting. SPI2 Serial peripheral interface with full-duplex or single-wire 256 K Flash comprised of two independent 128 K flash arrays bidirectional Double-buffered transmit and receive Master or Slave read/program/erase over full operating voltage and temperature mode MSB-first or LSB-first shifting. allows interrupt processing while programming. IIC Up to 100 kbps with maximum bus loading Multi-master 32 KB System Random-access memory (RAM). operation Programmable slave address Interrupt driven Security circuitry to prevent unauthorized access to RAM and byte-by-byte data transfer supports broadcast mode and 11-bit Flash contents. addressing. Power-Saving Modes CMT Carrier Modulator timer for remote control communications. Two ultra-low power stop modes. Peripheral clock enable register Carrier generator, modulator and driver for dedicated infrared out can disable clocks to unused modules to reduce currents. (IRO). Can be used as an output compare timer. Time of Day (TOD) Ultra low-power 1/4 sec counter with up to TPMx Two 4-channel Timer/PWM Module Selectable input 64 sec timeout. capture, output compare, or buffered edge- or center-aligned PWM Ultra-low power external oscillator that can be used in stop modes to on each channel external clock input/pulse accumulator. provide accurate clock source to the TOD. 6 s typical wake up Mini-FlexBus Multi-function external bus interface with user time from stop3 mode. programmable chip selects and the option to multiplex address and Clock Source Options data lines. Oscillator (XOSC1) Loop-control Pierce oscillator 32.768 kHz PRACMP Analog comparator with selectable interrupt compare crystal option to programmable internal reference voltage operation in or ceramic resonator dedicated for TOD operation. stop3. Oscillator (XOSC2) for high frequency crystal input for MCG Measurement Engine reference to be used for system clock and USB operations. ADC16 16-bit successive approximation ADC with up to 4 Multipurpose Clock Generator (MCG) PLL and FLL precision dedicated differential channels and 8 single-ended channels range trimming of internal reference allows 0.2% resolution and typical compare function 1.7 mV/C temperature sensor internal bandgap +0.5% reference channel operation in stop3 fully functional from 3.6 V to to -1% deviation over temperature and voltage supports CPU 1.8 V, Configurable hardware trigger for 8 Channel select and result frequencies from 4 kHz to 50 MHz. registers. System Protection PDB Programmable delay block with 16-bit counter and modulus Watchdog computer operating properly (COP) reset with option to and prescale to set reference clock to bus divided by 1 to bus divided run from dedicated 1 kHz internal clock source or bus clock. by 2048 8 trigger outputs for ADC module provides periodic Low-voltage detection with reset or interrupt selectable trip points coordination of ADC sampling sequence with sequence completion separate low voltage warning with optional interrupt selectable interrupt Back-to-Back mode and Timed mode. trip points. DAC 12-bit resolution DAC configurable settling time. Illegal opcode and illegal address detection with reset. OPAMPx 2 flexible operational amplifiers configurable for general Flash block protection for each array to prevent accidental write / operations Low offset and temperature drift. erasure. TRIAMPx 2 trans-impedance amplifiers dedicated for converting Hardware CRC to support fast cyclic redundancy checks. current inputs into voltages. Development Support Input/Output Integrated ColdFire DEBUG Rev B+ interface with single wire Up to 68 GPIOs and 1 output-only pin. BDM connection supports same electrical interface used by the Voltage Reference output (VREFO). S08 family debug modules. Dedicated infrared output pin (IRO)with high current sink capability. Real-time debug with 6 hardware breakpoints (4 PC, 1 address Up to 16 KBI pins with selectable polarity. and 1 data). Up to 16 pins of rapid general purpose I/O On-chip trace buffer provides programmable start/stop (RGPIO). recording conditions. Peripherals USB Dual-role USB On-The-Go (OTG) device, supports USB in either device, host or OTG configuration. On-chip transceiver and 3.3V regulator help save system cost, fully compliant with USB Specification Freescale Semiconductor, Inc., 2009-2012. All rights reserved.Table of Contents 1 Features 3 Figure 15.SPI Master Timing (CPHA = 0) . 44 2 Pinouts and Pin Assignments 8 Figure 16.SPI Master Timing (CPHA = 1) . 44 2.1 104-Pin MAPBGA .8 Figure 17.SPI Slave Timing (CPHA = 0) 45 2.2 100-Pin LQFP .9 Figure 18.SPI Slave Timing (CPHA = 1) 45 2.3 81-Pin MAPBGA 10 Figure 19.Typical VREF Output vs. Temperature 48 2.4 80-Pin LQFP .11 Figure 20.Typical VREF Output vs. V . 48 DD 2.5 Pin Assignments 12 List of Tables 3 Electrical Characteristics 17 Table 1. MCF51MM256/128 Features by MCU and Package 3 3.1 Parameter Classification 17 Table 2. MCF51MM256/128 Functional Units . 6 3.2 Absolute Maximum Ratings .17 Table 3. Package Pin Assignments . 12 3.3 Thermal Characteristics 18 Table 4. Parameter Classifications 17 3.4 ESD Protection Characteristics .20 Table 5. Absolute Maximum Ratings . 18 3.5 DC Characteristics 21 Table 6. Thermal Characteristics 19 3.6 Supply Current Characteristics .23 Table 7. ESD and Latch-up Test Conditions . 20 3.7 PRACMP Electrical Parameters 26 Table 8. ESD and Latch-Up Protection Characteristics . 20 3.8 12-Bit DAC Electrical Parameters .26 Table 9. DC Characteristics 21 3.9 ADC Characteristics .28 Table 10.Supply Current Characteristics 23 3.10 MCG and External Oscillator (XOSC) Characteristics .35 Table 11.Typical Stop Mode Adders 24 3.11 Mini-FlexBus Timing Specifications .38 Table 12.PRACMP Electrical Specifications . 26 3.12 AC Characteristics 39 Table 13.DAC 12LV Operating Requirements 26 3.13 SPI Characteristics 43 Table 14.DAC 12-Bit Operating Behaviors . 27 3.14 Flash Specifications .45 Table 15.16-bit ADC Operating Conditions 28 3.15 USB Electricals .46 Table 16.16-bit SAR ADC Characteristics full operating range 3.16 VREF Electrical Specifications .47 o (VREFH = VDDA > 1.8, VREFL = VSSA 8 Hz, -40 C to 3.17 TRIAMP Electrical Parameters .49 o 85 C) . 30 3.18 OPAMP Electrical Parameters .50 Table 17.16-bit SAR ADC Characteristics full operating range 4 Ordering Information 51 (VREFH = VDDA 2.7 V, VREFL = VSSA, f 4 MHz, 4.1 Part Numbers 51 ADACK ADHSC=1) 33 4.2 Package Information .52 o o Table 18.MCG (Temperature Range = 40 C to 105 C Ambient) 4.3 Mechanical Drawings 52 . 35 5 Revision History .53 o Table 19.XOSC Specifications (Temperature Range = 40 C to o List of Figures 105 C Ambient) . 37 Figure 1.MCF51MM256/128 Block Diagram 6 Table 20.Mini-FlexBus AC Timing Specifications 38 Figure 2.104-Pin MAPBGA . 8 Table 21.Control Timing . 40 Figure 3.100-Pin LQFP 9 Table 22.TPM Input Timing 41 Figure 4.81-Pin MAPBGA . 10 Table 23.SPI Timing 43 Figure 5.80-Pin LQFP 11 Table 24.Flash Characteristics 46 Figure 6.Stop IDD versus Temperature . 25 Table 25.Internal USB 3.3 V Voltage Regulator Characteristics 46 Figure 7.Offset at Half Scale vs Temperature 28 Table 26.VREF Electrical Specifications 47 Figure 8.ADC Input Impedance Equivalency Diagram . 30 Table 27.VREF Limited Range Operating Behaviors . 47 Figure 9.Mini-FlexBus Read Timing . 39 Table 28.TRIAMP Electrical Characteristics 1.8-3.6 V, -40C~105C Figure 10.Mini-FlexBus Write Timing 39 49 Figure 11.Reset Timing . 41 Table 29.OPAMP Characteristics 1.8-3.6 V 50 Figure 12.IRQ/KBIPx Timing . 41 Table 30.Orderable Part Number Summary 51 Figure 13.Timer External Clock . 42 Table 31.Package Descriptions . 52 Figure 14.Timer Input Capture Pulse 42 Table 32.Revision History 53 MCF51MM256/128, Rev. 5 2 Freescale Semiconductor