Freescale Semiconductor Document Number: MCF51QE128 Rev. 7, 10/2008 Data Sheet: Technical Data An Energy Efficient Solution by Freescale MCF51QE128 MCF51QE128 Series 80-LQFP 64-LQFP Covers: MCF51QE128, MCF51QE96, MCF51QE64, Case 917A Case 840F MCF51QE32 2 2 14 mm 10 mm 32-Bit Version 1 ColdFire Central Processor Unit (CPU) Development Support Up to 50.33-MHz ColdFire V1 CPU above 2.4V, Single-wire background debug interface 40-MHz CPU above 2.1V, and 20-MHz CPU above 4 PC plus 2 address (optional data) breakpoint registers 1.8V, across temperature range with programmable 1- or 2-level trigger response Provides 0.94 Dhrystone 2.1 MIPS per MHz 64-entry processor status and debug data trace buffer performance when running from internal RAM with programmable start/stop conditions (0.76 DMIPS/MHz from flash) ADC 24-channel, 12-bit resolution 2.5 s conversion Implements Instruction Set Revision C (ISA C) time automatic compare function 1.7 mV/C temperature Support for up to 30 peripheral interrupt requests and sensor internal bandgap reference channel operation in seven software interrupts stop3 fully functional from 3.6V to 1.8V On-Chip Memory ACMPx Two analog comparators with selectable Flash read/program/erase over full operating voltage interrupt on rising, falling, or either edge of comparator and temperature output compare option to fixed internal bandgap reference Random-access memory (RAM) voltage outputs can be optionally routed to TPM module Security circuitry to prevent unauthorized access to operation in stop3 RAM and flash contents SCIx Two SCIs with full duplex non-return to zero Power-Saving Modes (NRZ) LIN master extended break generation LIN slave Two low power stop modes reduced power wait mode extended break detection wake up on active edge Peripheral clock enable register can disable clocks to SPIx Two serial peripheral interfaces with Full-duplex or unused modules, reducing currents allows clocks to single-wire bidirectional Double-buffered transmit and remain enabled to specific peripherals in stop3 mode receive MSB-first or LSB-first shifting Very low power external oscillator can be used in stop3 IICx Two IICs with Up to 100 kbps with maximum bus mode to provide accurate clock to active peripherals loading Multi-master operation Programmable slave Very low power real time counter for use in run, wait, address Interrupt driven byte-by-byte data transfer and stop modes with internal and external clock sources supports broadcast mode and 10 bit addressing 6 s typical wake up time from stop modes TPMx One 6-channel and two 3-channel Selectable Clock Source Options input capture, output compare, or buffered edge- or Oscillator (XOSC) Loop-control Pierce oscillator center-aligned PWMs on each channel Crystal or ceramic resonator range of 31.25 kHz to RTC 8-bit modulus counter with binary or decimal 38.4 kHz or 1 MHz to 16 MHz based prescaler External clock source for precise time Internal Clock Source (ICS) FLL controlled by base, time-of-day, calendar or task scheduling functions internal or external reference precision trimming of Free running on-chip low power oscillator (1 kHz) for internal reference allows 0.2% resolution and 2% cyclic wake-up without external components deviation supports CPU freq. from 2 to 50.33 MHz Input/Output System Protection 70 GPIOs and 1 input-only and 1 output-only pin Watchdog computer operating properly (COP) reset 16 KBI interrupts with selectable polarity with option to run from dedicated 1-kHz internal clock Hysteresis and configurable pull-up device on all input source or bus clock pins Configurable slew rate and drive strength on all Low-voltage detection with reset or interrupt selectable output pins. trip points SET/CLR registers on 16 pins (PTC and PTE) Illegal opcode and illegal address detection with 16 bits of Rapid GPIO connected to the CPUs programmable reset or exception response high-speed local bus with set, clear, and toggle Flash block protection functionality Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Freescale Semiconductor, Inc., 2008. All rights reserved.Table of Contents 1 MCF51QE128 Series Comparison 4 3.10 AC Characteristics 21 2 Pin Assignments 5 3.10.1 Control Timing . 21 3 Electrical Characteristics .9 3.10.2 TPM Module Timing . 23 3.1 Introduction .9 3.10.3 SPI Timing 24 3.2 Parameter Classification .9 3.11 Analog Comparator (ACMP) Electricals . 27 3.3 Absolute Maximum Ratings 9 3.12 ADC Characteristics 27 3.4 Thermal Characteristics 10 3.13 Flash Specifications . 30 3.5 ESD Protection and Latch-Up Immunity 11 4 Ordering Information . 31 3.6 DC Characteristics 12 5 Package Information . 31 3.7 Supply Current Characteristics .15 5.1 Mechanical Drawings 31 3.8 External Oscillator (XOSC) Characteristics .18 6 Product Documentation . 36 3.9 Internal Clock Source (ICS) Characteristics .19 7 Revision History 36 MCF51QE128 Series Data Sheet, Rev. 7 2 Freescale Semiconductor