Freescale Semiconductor
Document Number: MCF53017
Rev. 5, 3/2010
Data Sheet: Advance Information
MCF53017
LQFP208 MAPBGA256
28 x 28 17 x 17
MCF5301x Data Sheet
Features
Version 3 ColdFire core with EMAC
Up to 211 Dhrystone 2.1 MIPS @ 240 MHz
16 KBytes unified instruction/data cache
128 KBytes internal SRAM with standby power supply
support
Crossbar switch technology (XBS) for concurrent access to
peripherals or RAM from multiple bus masters
Enhanced Secure Digital Host Controller (eSDHC)
Supports CE-ATA, SD Memory, miniSD Memory,
SDIO, miniSDIO, SD Combo, MMC, MMC plus, MMC
4x, and MMC RS cards
Two ISO7816 smart card interfaces
IC identification module
Voice-band audio codec with integrated speaker,
microphone, headphone, and handset amplifiers
16- or 32-bit SDR, 16-bit DDR/mobile-DDR SDRAM
controller
USB 2.0 On-the-Go controller
USB host controller
2 10/100 Ethernet MACs
Coprocessor for acceleration of the DES, 3DES, AES,
MD5, and SHA-1 algorithms
Random number generator
16-channel DMA controller
Synchronous serial interface
4 periodic interrupt timers
4 32-bit timers with DMA support
Real-time clock (RTC) module with standby support
DMA-supported serial peripheral interface (DSPI)
3 UARTs
2
I C bus interface
This document contains information on a new product. Specifications and information herein
are subject to change without notice.
Freescale Semiconductor, Inc., 2010. All rights reserved.
PreliminarySubject to Change Without NoticeTable of Contents
1 MCF5301x Family Comparison . . . . . . . . . . . . . . . . . . . . . . . .4 5.11 SSI Timing Specifications . . . . . . . . . . . . . . . . . . . . . . 34
2
2 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 5.12 I C Input/Output Timing Specifications . . . . . . . . . . . . 35
3 Hardware Design Considerations . . . . . . . . . . . . . . . . . . . . . . .5 5.13 Fast Ethernet AC Timing Specifications . . . . . . . . . . . 37
3.1 PLL Power Filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 5.13.1 Receive Signal Timing Specifications . . . . . . . 37
3.2 USB Power Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 5.13.2 Transmit Signal Timing Specifications . . . . . . . 37
3.3 Supply Voltage Sequencing . . . . . . . . . . . . . . . . . . . . . .6 5.13.3 Asynchronous Input Signal Timing Specifications38
3.3.1 Power Up Sequence . . . . . . . . . . . . . . . . . . . . . .7 5.13.4 MII Serial Management Timing Specifications . 38
3.3.2 Power Down Sequence . . . . . . . . . . . . . . . . . . . .7 5.14 32-Bit Timer Module Timing Specifications . . . . . . . . . 39
3.4 Power Consumption Specifications. . . . . . . . . . . . . . . . .8 5.15 DSPI Timing Specifications . . . . . . . . . . . . . . . . . . . . . 39
4 Pin Assignments and Reset States . . . . . . . . . . . . . . . . . . . . .9 5.16 eSDHC Electrical Specifications . . . . . . . . . . . . . . . . . 41
4.1 Signal Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 5.16.1 eSDHC Timing . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.2 Pinout208 LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 5.16.2 eSDHC Electrical DC Characterisics . . . . . . . . 42
4.3 Pinout256 MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . . .18 5.17 SIM Electrical Specifications . . . . . . . . . . . . . . . . . . . . 43
5 Preliminary Electrical Characteristics . . . . . . . . . . . . . . . . . . .19 5.17.1 General Timing Requirements . . . . . . . . . . . . . 43
5.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 5.17.2 Reset Sequence. . . . . . . . . . . . . . . . . . . . . . . . 44
5.2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .20 5.17.3 Power Down Sequence . . . . . . . . . . . . . . . . . . 45
5.3 ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 5.18 IIM/Fusebox Electrical Specifications . . . . . . . . . . . . . 46
5.4 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . .21 5.19 Voice Codec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
5.4.1 PLL Power Filtering . . . . . . . . . . . . . . . . . . . . . .22 5.19.1 Voice Codec ADC Specifications . . . . . . . . . . . 47
5.4.2 USB Power Filtering. . . . . . . . . . . . . . . . . . . . . .22 5.19.2 Voice Codec DAC Specifications . . . . . . . . . . . 51
5.4.3 Supply Voltage Sequencing and Separation 5.20 Integrated Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Cautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 5.20.1 Speaker Amplifier. . . . . . . . . . . . . . . . . . . . . . . 55
5.5 Oscillator and PLL Electrical Characteristics . . . . . . . .24 5.20.2 Handset Amplifier. . . . . . . . . . . . . . . . . . . . . . . 56
5.6 External Interface Timing Characteristics . . . . . . . . . . .25 5.20.3 Headphone Amplifier . . . . . . . . . . . . . . . . . . . . 57
5.6.1 FlexBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 5.20.4 Microphone Amplifier . . . . . . . . . . . . . . . . . . . . 57
5.7 SDRAM Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 5.21 JTAG and Boundary Scan Timing . . . . . . . . . . . . . . . . 58
5.7.1 SDR SDRAM AC Timing Characteristics. . . . . .27 5.22 Debug AC Timing Specifications . . . . . . . . . . . . . . . . . 60
5.7.2 DDR SDRAM AC Timing Characteristics . . . . .30 6 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
5.8 General Purpose I/O Timing . . . . . . . . . . . . . . . . . . . . .32 7 Product Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
5.9 Reset and Configuration Override Timing. . . . . . . . . . .33 8 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
5.10 USB On-The-Go . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
MCF5301x Data Sheet, Rev. 5
2 PreliminarySubject to Change Without Notice Freescale Semiconductor