Freescale Semiconductor
Document Number: MCF5475EC
Rev. 4, 12/2007
Data Sheet
MCF547x
MCF547x ColdFire
TEPBGA388
Microprocessor
27 mm x 27 mm
Supports MCF5470, MCF5471,
MCF5472, MCF5473, MCF5474, and
MCF5475
Features list:
endpoints, interrupt, bulk, or isochronous
ColdFire V4e Core 4-Kbytes of shared endpoint FIFO RAM and 1 Kbyte
Limited superscalar V4 ColdFire processor core of endpoint descriptor RAM
Up to 266 MHz peak internal core frequency (410 MIPS Integrated physical layer interface
[Dhrystone 2.1] @ 266 MHz) Up to four programmable serial controllers (PSCs) each
Harvard architecture with separate 512-byte receive and transmit FIFOs for
32-Kbyte instruction cache UART, USART, modem, codec, and IrDA 1.1 interfaces
2
32-Kbyte data cache I C peripheral interface
Memory Management Unit (MMU) DMA Serial Peripheral Interface (DSPI)
Separate, 32-entry, fully-associative instruction and Optional Cryptography accelerator module
data translation lookahead buffers Execution units for:
Floating point unit (FPU) DES/3DES block cipher
Double-precision conforms to IEE-754 standard AES block cipher
Eight floating point registers RC4 stream cipher
Internal master bus (XLB) arbiter MD5/SHA-1/SHA-256/HMAC hashing
High performance split address and data transactions Random Number Generator
Support for various parking modes 32-Kbyte system SRAM
32-bit double data rate (DDR) synchronous DRAM Arbitration mechanism shares bandwidth between
(SDRAM) controller internal bus masters
66133 MHz operation System integration unit (SIU)
Supports DDR and SDR DRAM Interrupt controller
Built-in initialization and refresh Watchdog timer
Up to four chip selects enabling up to one GB of external Two 32-bit slice timers alarm and interrupt generation
memory Up to four 32-bit general-purpose timers, compare, and
Version 2.2 peripheral component interconnect (PCI) bus PWM capability
32-bit target and initiator operation GPIO ports multiplexed with peripheral pins
Support for up to five external PCI masters Debug and test features
3366 MHz operation with PCI bus to XLB divider ColdFire background debug mode (BDM) port
ratios of 1:1, 1:2, and 1:4 JTAG/ IEEE 1149.1 test access port
Flexible multi-function external bus (FlexBus) PLL and clock generator
Provides a glueless interface to boot flash/ROM, 30 to 66.67 MHz input frequency range
SRAM, and peripheral devices Operating Voltages
Up to six chip selects 1.5V internal logic
33 66 MHz operation 2.5V DDR SDRAM bus I/O
Communications I/O subsystem 3.3V PCI, FlexBus, and all other I/O
Intelligent 16 channel DMA controller Estimated power consumption
Up to two 10/100 Mbps fast Ethernet controllers (FECs) Less than 1.5W (388 PBGA)
each with separate 2-Kbyte receive and transmit FIFOs
Universal serial bus (USB) version 2.0 device controller
Support for one control and six programmable
Freescale Semiconductor, Inc., 2007. All rights reserved.Table of Contents
1 Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Figure 15.DDR Clock Timing Diagram. . . . . . . . . . . . . . . . . . . . 18
2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Figure 16.DDR Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.1 Operating Temperatures . . . . . . . . . . . . . . . . . . . . . . . . .4 Figure 17.DDR Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.2 Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Figure 18.PCI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Figure 19.MII Receive Signal Timing Diagram. . . . . . . . . . . . . . 23
4 Hardware Design Considerations . . . . . . . . . . . . . . . . . . . . . . .6 Figure 20.MII Transmit Signal Timing Diagram . . . . . . . . . . . . . 23
4.1 PLL Power Filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Figure 21.MII Async Inputs Timing Diagram . . . . . . . . . . . . . . . 24
4.2 Supply Voltage Sequencing and Separation Cautions . .6 Figure 22.MII Serial Management Channel TIming Diagram. . . 24
2
4.3 General USB Layout Guidelines . . . . . . . . . . . . . . . . . . .8 Figure 23.I C Input/Output Timings . . . . . . . . . . . . . . . . . . . . . . 26
4.4 USB Power Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Figure 24.Test Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . 27
5 Output Driver Capability and Loading. . . . . . . . . . . . . . . . . . .10 Figure 25.Boundary Scan (JTAG) Timing . . . . . . . . . . . . . . . . . 27
6 PLL Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Figure 26.Test Access Port Timing . . . . . . . . . . . . . . . . . . . . . . 27
7 Reset Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . .12 Figure 27.TRST Timing Debug AC Timing Specifications . . . . . 27
8 FlexBus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Figure 28.Real-Time Trace AC Timing. . . . . . . . . . . . . . . . . . . . 28
8.1 FlexBus AC Timing Characteristics. . . . . . . . . . . . . . . .13 Figure 29.BDM Serial Port AC Timing . . . . . . . . . . . . . . . . . . . . 28
9 SDRAM Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Figure 30.DSPI Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
9.1 SDR SDRAM AC Timing Characteristics . . . . . . . . . . .15 Figure 31.388-pin BGA Case Outline. . . . . . . . . . . . . . . . . . . . . 31
9.2 DDR SDRAM AC Timing Characteristics . . . . . . . . . . .18
List of Tables
10 PCI Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Table 1. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . 4
11 Fast Ethernet AC Timing Specifications . . . . . . . . . . . . . . . . .22
Table 2. Operating Temperatures . . . . . . . . . . . . . . . . . . . . . . . . 4
11.1 MII/7-WIRE Interface Timing Specs . . . . . . . . . . . . . . .22
Table 3. Thermal Resistance. . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
11.2 MII Transmit Signal Timing . . . . . . . . . . . . . . . . . . . . . .23
Table 4. DC Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . 5
11.3 MII Async Inputs Signal Timing (CRS, COL) . . . . . . . .24
Table 5. USB Filter Circuit Values . . . . . . . . . . . . . . . . . . . . . . . . 9
11.4 MII Serial Management Channel Timing (MDIO,MDC).24
Table 6. I/O Driver Capability . . . . . . . . . . . . . . . . . . . . . . . . . . 10
12 General Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . .25
2
Table 7. Clock Timing Specifications. . . . . . . . . . . . . . . . . . . . . 11
13 I C Input/Output Timing Specifications. . . . . . . . . . . . . . . . . .25
Table 8. MCF547x Divide Ratio Encodings. . . . . . . . . . . . . . . . 11
14 JTAG and Boundary Scan Timing. . . . . . . . . . . . . . . . . . . . . .26
Table 9. Reset Timing Specifications . . . . . . . . . . . . . . . . . . . . 12
15 DSPI Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . .29
Table 10.FlexBus AC Timing Specifications. . . . . . . . . . . . . . . . 13
16 Timer Module AC Timing Specifications. . . . . . . . . . . . . . . . .29
Table 11.SDR Timing Specifications . . . . . . . . . . . . . . . . . . . . . 16
17 Case Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Table 12.DDR Clock Crossover Specifications . . . . . . . . . . . . . 18
18 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Table 13.DDR Timing Specifications . . . . . . . . . . . . . . . . . . . . . 18
List of Figures
Table 14.PCI Timing Specifications . . . . . . . . . . . . . . . . . . . . . . 21
Figure 1.MCF547X Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 3 Table 15.MII Receive Signal Timing. . . . . . . . . . . . . . . . . . . . . . 23
Figure 2.System PLL V Power Filter . . . . . . . . . . . . . . . . . . . . 6 Table 16.MII Transmit Signal Timing . . . . . . . . . . . . . . . . . . . . . 23
DD
Figure 3.Supply Voltage Sequencing and Separation Cautions . 7 Table 17.MII Transmit Signal Timing . . . . . . . . . . . . . . . . . . . . . 24
Figure 4.Preferred VBUS Connections . . . . . . . . . . . . . . . . . . . . 8 Table 18.MII Serial Management Channel Signal Timing . . . . . 24
Figure 5.Alternate VBUS Connections . . . . . . . . . . . . . . . . . . . . 8 Table 19.General AC Timing Specifications. . . . . . . . . . . . . . . . 25
2
Figure 6.USB V Power Filter . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 20.I C Input Timing Specifications between
DD
Figure 7.USBRBIAS Connection. . . . . . . . . . . . . . . . . . . . . . . . 10 SCL and SDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2
Figure 8.Input Clock Timing Diagram . . . . . . . . . . . . . . . . . . . . 11 Table 21. I C Output Timing Specifications between
Figure 9.CLKIN, Internal Bus, and Core Clock Ratios . . . . . . . 11 SCL and SDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 10.Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 22.JTAG and Boundary Scan Timing . . . . . . . . . . . . . . . . 26
Figure 11.FlexBus Read Timing . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 23.Debug AC Timing Specifications . . . . . . . . . . . . . . . . . 28
Figure 12.FlexBus Write Timing . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 24.DSPI Modules AC Timing Specifications. . . . . . . . . . . 29
Figure 13.SDR Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 25.Timer Module AC Timing Specifications . . . . . . . . . . . 29
Figure 14.SDR Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
MCF547x ColdFire Microprocessor, Rev. 4
2 Freescale Semiconductor