Document Number: MC33903 4 5 Freescale Semiconductor Rev. 11.0, 8/2014 Technical Data SBC Gen2 with CAN High Speed 33903/ 33903/4/5 and LIN Interface The 33903/4/5 is the second generation family of the System Basis Chip (SBC). It combines several features and enhances present module designs. The device works as an advanced power SYSTEM BASIS CHIP management unit for the MCU with additional integrated circuits such as sensors and CAN transceivers. It has a built-in enhanced high-speed CAN interface (ISO11898-2 and -5) with local and bus failure diagnostics, protection, and fail-safe operation modes. The SBC may include zero, one or two LIN 2.1 interfaces with LIN output pin switches. It includes up to four wake-up input pins that can also be configured as output drivers for flexibility. This device is powered by SMARTMOS technology. This device implements multiple Low-power (LP) modes, with very EK Suffix (Pb-free) EK Suffix (Pb-free) low-current consumption. In addition, the device is part of a family 98ASA10506D 98ASA10556D 54-PIN SOIC concept where pin compatibility adds versatility to module design. 32-PIN SOIC The 33903/4/5 also implements an innovative and advanced fail-safe state machine and concept solution. Applications Aircraft and marine systems Features Automotive and robotic systems Voltage regulator for MCU, 5.0 or 3.3 V, part number selectable, with Farm equipment possibility of usage external PNP to extend current capability and Industrial actuator controls share power dissipation Lamp and inductive load controls Voltage, current, and temperature protection DC motor control applications requiring diagnostics Extremely low quiescent current in LP modes Applications where high-side switch control is Fully-protected embedded 5.0 V regulator for the CAN driver required Multiple undervoltage detections to address various MCU specifications and system operation modes (i.e. cranking) Auxiliary 5.0 or 3.3 V SPI configurable regulator, for additional ICs, with overcurrent detection and undervoltage protection MUX output pin for device internal analog signal monitoring and power supply monitoring Advanced SPI, MCU, ECU power supply, and critical pins diagnostics and monitoring. Multiple wake-up sources in LP modes: CAN or LIN bus, I/O transition, automatic timer, SPI message, and V overcurrent DD detection. ISO11898-5 high-speed CAN interface compatibility for baud rates of 40 kb/s to 1.0 Mb/s Scalable product family of devices ranging from 0 to 2 LINs which are compatible to J2602-2 and LIN 2.1 Freescale Semiconductor, Inc., 2010 - 2014. All rights reserved.TABLE OF CONTENTS TABLE OF CONTENTS Simplified Application Diagrams ................................................................................................................. 3 Device Variations ....................................................................................................................................... 7 Internal Block Diagrams ............................................................................................................................. 9 Pin Connections ....................................................................................................................................... 11 Electrical Characteristics .......................................................................................................................... 17 Maximum Ratings .................................................................................................................................. 17 Static Electrical Characteristics ............................................................................................................. 19 Dynamic Electrical Characteristics ........................................................................................................ 27 Timing Diagrams ................................................................................................................................... 30 Functional Description .............................................................................................................................. 35 Introduction ............................................................................................................................................ 35 Functional Pin Description ..................................................................................................................... 35 Functional Device Operation .................................................................................................................... 39 Mode and State Description .................................................................................................................. 39 LP Modes .............................................................................................................................................. 40 State Diagram ........................................................................................................................................ 41 Mode Change ........................................................................................................................................ 42 Watchdog Operation .............................................................................................................................. 42 Functional Block Operation Versus Mode ............................................................................................. 44 Illustration of Device Mode Transitions................................................................................................ 45 Cyclic Sense Operation During LP Modes ............................................................................................ 47 Behavior at Power Up and Power Down ............................................................................................... 49 Fail-safe Operation ................................................................................................................................... 51 CAN Interface ........................................................................................................................................ 55 CAN Interface Description ..................................................................................................................... 55 CAN Bus Fault Diagnostic ..................................................................................................................... 58 LIN Block .................................................................................................................................................. 61 LIN Interface Description ....................................................................................................................... 61 LIN Operational Modes .......................................................................................................................... 61 Serial Peripheral Interface ........................................................................................................................ 63 High Level Overview .............................................................................................................................. 63 Detail Operation ..................................................................................................................................... 64 Detail of Control Bits And Register Mapping ......................................................................................... 67 Flags and Device Status ........................................................................................................................ 84 Typical Applications ................................................................................................................................. 91 Packaging ................................................................................................................................................ 99 33903/4/5 Analog Integrated Circuit Device Data 2 Freescale Semiconductor