MPC5200 Freescale Semiconductor Rev. 4, 01/2005 Data Sheet MPC5200 Data Sheet Table of Contents NOTE 1 Overview 1 The information in this 2 Features 2 document is subject to 3 Electrical and Thermal Characteristics . 6 change. For the latest data 3.1 DC Electrical Characteristics . 6 on the MPC5200, visit 3.2 Oscillator and PLL Electrical Characteristics . 12 www.freescale.com and 3.3 AC Electrical Characteristics 14 proceed to the MPC5200 4 Package Description 64 Product Summary Page. 4.1 Package Parameters 64 4.2 Mechanical Dimensions 64 4.3 Pinout Listings . 66 5 System Design Information . 71 1 Overview 5.1 Power UP/Down Sequencing . 71 5.2 System and CPU Core AVDD power The MPC5200 integrates a high performance MPC603e supply filtering . 73 series G2 LE core with a rich set of peripheral functions 5.3 Pull-up/Pull-down Resistor Requirements 73 focused on communications and systems integration. 5.4 JTAG 74 TM 6 Ordering Information 79 The G2 LE core design is based on the PowerPC core 7 Document Revision History . 79 architecture. MPC5200 incorporates an innovative BestComm I/O subsystem, which isolates routine maintenance of peripheral functions from the embedded G2 LE core. The MPC5200 contains a SDRAM/DDR Memory Controller, a flexible External Bus Interface, PCI Controller, USB, ATA, Ethernet, six Programmable 2 Serial Controllers (PSC), I C, SPI, CAN, J1850, Timers, and GPIOs. Definitive Data: Freescale reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products. Freescale Semiconductor, Inc., 2005, 2006. All rights reserved.Features 2Features Key features are shown below. MPC603e series G2 LE core Superscalar architecture o 760 MIPS at 400 MHz (-40 to +85 C) 16 k Instruction cache, 16 k Data cache Double precision FPU Instruction and Data MMU Standard and Critical interrupt capability SDRAM / DDR Memory Interface up to 132-MHz operation SDRAM and DDR SDRAM support 256-MByte addressing range per CS, two CS available 32-bit data bus Built-in initialization and refresh Flexible multi-function External Bus Interface Supports interfacing to ROM/Flash/SRAM memories or other memory mapped devices 8 programmable Chip Selects Non multiplexed data access using 8/16/32 bit databus with up to 26-bit address Short or Long Burst capable Multiplexed data access using 8/16/32 bit databus with up to 25-bit address Peripheral Component Interconnect (PCI) Controller Version 2.2 PCI compatibility PCI initiator and target operation 32-bit PCI Address/Data bus 33- and 66-MHz operation PCI arbitration function ATA Controller Version 4 ATA compatible external interfaceIDE Disk Drive connectivity BestComm DMA subsystem Intelligent virtual DMA Controller Dedicated DMA channels to control peripheral reception and transmission Local memory (SRAM 16 kBytes) 6 Programmable Serial Controllers (PSC), configurable for the following: UART or RS232 interface MPC5200 Data Sheet, Rev. 4 2 Freescale Semiconductor