Document Number: MPC603E7TEC Freescale Semiconductor Rev. 5, 09/2011 Technical Data PowerPC 603e RISC Microprocessor Family: PID7t-603e Hardware Specifications Contents The PowerPC 603e microprocessor is an implementation 1. Overview . 2 of the PowerPC family of reduced instruction set computing 2. Features 3 (RISC) microprocessors. In this document, the term 603e 3. General Parameters . 4 is used as an abbreviation for the PowerPC 603e 4. Electrical and Thermal Characteristics 4 5. Pin Assignments 14 microprocessor. The PowerPC 603e microprocessors are 6. Pinout Listings . 15 available from Freescale as MPC603e. 7. Package Descriptions 17 8. System Design Information 20 The 603e is implemented in several semiconductor 9. Ordering Information 29 fabrication processes. Different processes may require 10. Revision History 30 different supply voltages and may have other electrical differences but will have the same functionality. As a technical designator to distinguish between 603e implementations in various processes, a prefix composed of the processor version register (PVR) value and a process identifier (PID) is assigned to the various implementations as shown in Table 1. This document describes the pertinent physical characteristics of the PID7t-603e from Freescale. For functional characteristics of the 603e, refer to the PowerPC 603e RISC Microprocessor Users Manual. To locate any published errata or updates for this document, refer to the website at www.freescale.com. Freescale Semiconductor, Inc., 2011. All rights reserved.Overview Table 1. PowerPC 603e Microprocessors from Freescale Technical Core Voltage I/O Voltage 5-Volt Process Part Number Designator (V) (V) Tolerant PID6-603e 0.5 m CMOS, 4LM 3.3 3.3 Yes MPC603E PID7v-603e 0.35 m CMOS, 5LM 2.5 3.3 Yes XPC603P (end-of-life) PID7t-603e 0.29 m CMOS, 5LM 2.5 3.3 Yes MPC603R 1 Overview The 603e is a low-power implementation of the PowerPC microprocessor family of RISC microprocessors. The 603e implements the 32-bit portion of the PowerPC architecture specification that provides 32-bit effective addresses, integer data types of 8, 16, and 32 bits, and floating-point data types of 32 and 64 bits. For 64-bit PowerPC microprocessors, the PowerPC architecture provides 64-bit integer data types, 64-bit addressing, and other features required to complete the 64-bit architecture. The 603e provides four software controllable power-saving modes. Three of the modes (the nap, doze, and sleep) are static in nature, and progressively reduce the amount of power dissipated by the processor. The fourth is a dynamic power management mode that causes the functional units in the 603e to automatically enter a low-power mode when the functional units are idle without affecting operational performance, software execution, or any external hardware. The 603e is a superscalar processor capable of issuing and retiring as many as three instructions per clock. Instructions can execute out of order for increased performance however, the 603e makes completion appear sequential. The 603e integrates five execution unitsan integer unit (IU), a floating-point unit (FPU), a branch processing unit (BPU), a load/store unit (LSU), and a system register unit (SRU). The ability to execute five instructions in parallel and the use of simple instructions with rapid execution times yield high efficiency and throughput for 603e-based systems. Most integer instructions execute in one clock cycle. The FPU is pipelined, so a single-precision multiply-add instruction can be issued every clock cycle. The 603e provides independent on-chip, 16-Kbyte, four-way set-associative, physically addressed caches for instructions and data and on-chip instruction and data memory management units (MMUs). The MMUs contain 64-entry, two-way, set-associative data and instruction translation lookaside buffers (DTLB and ITLB) that provide support for demand-paged virtual memory address translation and variable-sized block translation. The TLBs and caches use a least-recently used (LRU) replacement algorithm. The 603e also supports block address translation through the use of two independent instruction and data block address translation (IBAT and DBAT) arrays of four entries each. Effective addresses are compared simultaneously with all four entries in the BAT array during block translation. In accordance with the PowerPC architecture, if an effective address hits in both the TLB and BAT array, the BAT translation takes priority. The 603e has a selectable 32- or 64-bit data bus and a 32-bit address bus. The 603e interface protocol allows multiple masters to compete for system resources through a central external arbiter. The 603e provides a three-state coherency protocol that supports the exclusive, modified, and invalid cache states. This protocol is a compatible subset of the MESI (modified/exclusive/shared/invalid) four-state protocol PID7t-603e Hardware Specifications, Rev. 5 2 Freescale Semiconductor