Document Number:MPC8306EC Freescale Semiconductor Rev. 3,12/2014 Technical Data MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications Contents This document provides an overview of the MPC8306 1. Overview . 2 PowerQUICC II Pro processor features. The MPC8306 is a 2. Electrical Characteristics 7 cost-effective, highly integrated communications processor 3. Power Characteristics 10 that addresses the requirements of several networking 4. Clock Input Timing 11 5. RESET Initialization . 12 applications, including residential gateways, 6. DDR2 SDRAM . 13 modem/routers, industrial control, and test and measurement 7. Local Bus . 18 applications. The MPC8306 extends current PowerQUICC 8. Ethernet and MII Management . 21 9. TDM/SI . 29 offerings, adding higher CPU performance, additional 10. HDLC 30 functionality, and faster interfaces, while addressing the 11. USB 33 requirements related to time-to-market, price, power 12. DUART . 35 consumption, and board real estate. This document describes 13. eSDHC . 36 14. FlexCAN 38 the electrical characteristics of MPC8306. 2 15. I C . 39 To locate published errata or updates for this document, refer 16. Timers 41 17. GPIO . 42 to the MPC8306 product summary page on our website 18. IPIC 43 listed on the back cover of this document or contact your 19. SPI . 43 local Freescale sales office. 20. JTAG . 45 21. Package and Pin Listings . 49 22. Clocking 59 23. Thermal . 66 24. System Design Information . 69 25. Ordering Information 72 26. Document Revision History . 74 2011, 2014 Freescale Semiconductor, Inc. All rights reserved. Overview 1 Overview The MPC8306 incorporates the e300c3 (MPC603e-based) core built on Power Architecture technology, which includes 16 Kbytes of each L1 instruction and data caches, dual integer units, and on-chip memory management units (MMUs). The MPC8306 also includes two DMA engines and a 16-bit DDR2 memory controller. A new communications complex based on QUICC Engine technology forms the heart of the networking capability of the MPC8306. The QUICC Engine block contains several peripheral controllers and a 32-bit RISC controller. Protocol support is provided by the main workhorses of the devicethe unified communication controllers (UCCs). A block diagram of the MPC8306 is shown in the following figure. 2x DUART e300c3 Core with Power I2C Management Timers 16-KB 16-KB GPIO I-Cache D-Cache ULPI SPI Enhanced Local Interrupt DDR2 RTC USB 2.0 HS FPU Controller Bus Controller Controller Host/Device/OTG DMA eSDHC 4 FlexCAN QUICC Engine Block Engine 16 KB Multi-User RAM Accelerators 48 KB Instruction RAM Baud Rate Generators Serial DMA Single 32-bit RISC CP Time Slot Assigner Serial Interface 1 RMII/MII 2x TDM Ports 2 RMII/MII 2x IEEE 1588 2x HDLC Figure 1. MPC8306 Block Diagram Each of the five UCCs can support a variety of communication protocols such as 10/100 Mbps MII/RMII Ethernet, IEEE-1588, HDLC and TDM. MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 2 Freescale Semiconductor UCC1 UCC2 UCC3 UCC5 UCC7