Document Number: MPC8313EEC Freescale Semiconductor Rev. 4, 11/2011 Datasheet: Technical Data MPC8313E PowerQUICC II Pro Processor Hardware Specifications Contents This document provides an overview of the MPC8313E 1. Overview . 2 PowerQUICC II Pro processor features, including a block 2. Electrical Characteristics 6 diagram showing the major functional components. The 3. Power Characteristics 11 MPC8313E is a cost-effective, low-power, highly integrated 4. Clock Input Timing 12 5. RESET Initialization . 13 host processor that addresses the requirements of several 6. DDR and DDR2 SDRAM . 14 printing and imaging, consumer, and industrial applications, 7. DUART . 21 including main CPUs and I/O processors in printing systems, 8. Ethernet: Three-Speed Ethernet, MII Management . 21 9. High-Speed Serial Interfaces (HSSI) 36 networking switches and line cards, wireless LANs 10. USB 45 (WLANs), network access servers (NAS), VPN routers, 11. Enhanced Local Bus . 47 intelligent NIC, and industrial controllers. The MPC8313E 12. JTAG . 51 2 extends the PowerQUICC family, adding higher CPU 13. I C . 54 14. PCI 56 performance, additional functionality, and faster interfaces 15. Timers 58 while addressing the requirements related to time-to-market, 16. GPIO . 59 price, power consumption, and package size. 17. IPIC 61 18. SPI . 61 NOTE 19. Package and Pin Listings . 63 20. Clocking 77 The information in this document is accurate for 21. Thermal . 82 revisions 1.0, 2.x, and later. See Section 23.1, Part 22. System Design Information . 87 Numbers Fully Addressed by this Document. 23. Ordering Information 93 24. Revision History 95 Freescale Semiconductor, Inc., 20072011. All rights reserved.1 Overview The MPC8313E incorporates the e300c3 core, which includes 16 Kbytes of L1 instruction and data caches and on-chip memory management units (MMUs). The MPC8313E has interfaces to dual enhanced three-speed 10/100/1000 Mbps Ethernet controllers, a DDR1/DDR2 SDRAM memory controller, an enhanced local bus controller, a 32-bit PCI controller, a dedicated security engine, a USB 2.0 dual-role 2 controller and an on-chip high-speed PHY, a programmable interrupt controller, dual I C controllers, a 4-channel DMA controller, and a general-purpose I/O port. This figure shows a block diagram of the MPC8313E. DUART e300c3 Core w/FPU and 2 Dual I C Power Management Timers Interrupt 16-KB 16-KB Local Bus, DDR1/DDR2 GPIO I-Cache D-Cache SPI Controller Controller USB 2.0 Gb Ethernet Gb Ethernet Security Engine 2.2 I/O Sequencer Host/Device/OTG MAC MAC (IOS) On-Chip ULPI FS PHY PCI DMA Note: The MPC8313 does not include a security engine. Figure 1. MPC8313E Block Diagram The MPC8313E security engine (SEC 2.2) allows CPU-intensive cryptographic operations to be offloaded from the main CPU core. The security-processing accelerator provides hardware acceleration for the DES, 3DES, AES, SHA-1, and MD-5 algorithms. 1.1 MPC8313E Features The following features are supported in the MPC8313E: Embedded PowerPC e300 processor core built on Power Architecture technology operates at up to 333 MHz. High-performance, low-power, and cost-effective host processor DDR1/DDR2 memory controllerone 16-/32-bit interface at up to 333 MHz supporting both DDR1 and DDR2 16-Kbyte instruction cache and 16-Kbyte data cache, a floating point unit, and two integer units Peripheral interfaces such as 32-bit PCI interface with up to 66-MHz operation, 16-bit enhanced local bus interface with up to 66-MHz operation, and USB 2.0 (high speed) with an on-chip PHY. Security engine provides acceleration for control and data plane security protocols Power management controller for low-power consumption High degree of software compatibility with previous-generation PowerQUICC processor-based designs for backward compatibility and easier software migration MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 2 Freescale Semiconductor