Document Number: MPC8314EEC Freescale Semiconductor Rev. 2, 11/2011 Data Sheet: Technical Data MPC8314E PowerQUICC II Pro Processor Hardware Specifications Contents This document provides an overview of the MPC8314E 1. Overview . 2 PowerQUICC II Pro processor features, including a block 2. MPC8314E Features 2 diagram showing the major functional components. The 3. Electrical Characteristics 7 MPC8314E contains a core built on Power Architecture 4. Power Characteristics 12 5. Clock Input Timing 13 technology. It is a cost-effective, low-power, highly 6. RESET Initialization . 15 integrated host processor that addresses the requirements of 7. DDR and DDR2 SDRAM . 16 several storage, consumer, and industrial applications, 8. DUART . 22 9. Ethernet: Three-Speed Ethernet, MII Management . 22 including main CPUs and I/O processors in network attached 10. USB 37 storage (NAS), voice over IP (VoIP) router/gateway, 11. Local Bus . 39 intelligent wireless LAN (WLAN), set top boxes, industrial 12. JTAG . 42 2 controllers, and wireless access points. The MPC8314E 13. I C . 45 14. PCI 47 extends the PowerQUICC II Pro family, adding higher CPU 15. High-Speed Serial Interfaces (HSSI) 49 performance, new functionality, and faster interfaces while 16. PCI Express 59 addressing the requirements related to time-to-market, price, 17. Timers 66 18. GPIO . 67 power consumption, and package size. Note that while the 19. IPIC 68 MPC8314E supports a security engine, the MPC8314 does 20. SPI . 68 not. 21. TDM . 70 22. Package and Pin Listings . 72 23. Clocking 85 24. Thermal . 90 25. System Design Information . 95 26. Ordering Information 98 27. Revision History . 100 Freescale Semiconductor, Inc., 2011. All rights reserved.Overview 1 Overview The MPC8314E incorporates the e300c3 (MPC603e-based) core, which includes 16 Kbytes of L1 instruction and data caches, on-chip memory management units (MMUs), and floating-point support. In addition to the e300 core, the SoC platform includes features such as dual enhanced three-speed 10, 100, 1000 Mbps Ethernet controllers (eTSECs) with SGMII support, a 32- or 16-bit DDR1/DDR2 SDRAM memory controller, a security engine to accelerate control and data plane security protocols, and a high degree of software compatibility with previous-generation PowerQUICC processor-based designs for backward compatibility and easier software migration. The MPC8314E also offers peripheral interfaces such as a 32-bit PCI interface with up to 66 MHz operation, 16-bit enhanced local bus interface with up to 66 MHz operation, TDM interface, and USB 2.0 with an on-chip USB 2.0 PHY. 8314E offers additional high-speed interconnect support with dual single-lane PCI Express interfaces. When not used for PCI Express, the SerDes interface may be configured to support SGMII. The MPC8314E security engine (SEC 3.3) allows CPU-intensive cryptographic operations to be offloaded from the main CPU core. This figure shows a block diagram of the MPC8314E. MPC8314E e300c3 Core with Power Management 16-KB 16-KB DUART I-Cache D-Cache 2 I C Enhanced Interrupt DDR1/DDR2 Timers Security Local Bus, FPU Controller TDM Engine 3.3 Controller GPIO SPI I/O USB 2.0 HS PCI PCI Sequencer eTSEC eTSEC Host/Device/OTG Express Express (IOS) x1 On-Chip RGMII, (R)MII x1 RGMII, (R)MII ULPI RTBI, SGMII HS PHY RTBI, SGMII PCI DMA Note: The MPC8314 do not include a security engine. Figure 1. MPC8314E Block Diagram 2 MPC8314E Features The following features are supported in the MPC8314E. 2.1 e300 Core The e300 core has the following features: Operates at up to 400 MHz 16-Kbyte instruction cache, 16-Kbyte data cache MPC8314E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2 2 Freescale Semiconductor