Freescale Semiconductor
Document Number: MPC8536EEC
Data Sheet: Technical Data Rev. 5, 09/2011
MPC8536E
MPC8536E PowerQUICC III
Integrated Processor
MAPBGA783
29 mm x 29 mm
Hardware Specifications
High-performance, 32-bit e500 core, scaling up to Support for various Ethernet physical interfaces: GMII,
1.5 GHz, that implements the Power Architecture TBI, RTBI, RGMII, MII, RGMII, RMII, and SGMII
technology Support TCP/IP acceleration and QOS features
36-bit physical addressing MAC address recognition and RMON statistics support
Double-precision embedded floating point APU using Support ARP parsing and generating wake-up events
64-bit operands based on the parsing results while in deep sleep mode
Embedded vector and scalar single-precision Support accepting and storing packets while in deep
floating-point APUs using 32- or 64-bit operands sleep mode
Memory management unit (MMU) High-speed interfaces (multiplexed) supporting:
Integrated L1/L2 cache Three PCI Express interfaces
L1 cache32-Kbyte data and 32-Kbyte instruction PCI Express 1.0a compatible
L2 cache512-Kbyte (8-way set associative)
One x8/x4/x2/x1 PCI Express interface
DDR2/DDR3 SDRAM memory controller with full ECC
Two x4/x2/x1 ports, or,
support
One x4/x2/x1 port and Two x2/x1 ports
One 64-bit/32-bit data bus
Two SGMII interfaces
Up to 333-MHz clock (667-MHz data rate)
Two Serial ATA (SATA) controllers support SATA I and
Supporting up to 16 Gbytes of main memory
SATA I data rates
Using ECC, detects and corrects all single-bit errors and
PCI 2.2 compatible PCI controller
detects all double-bit errors and all errors within a nibble
Three universal serial bus (USB) dual-role controllers
Invoke a level of system power management by
comply with USB specification revision 2.0
asserting MCKE SDRAM signal on-the-fly to put the
133-MHz, 32-bit, enhanced local bus (eLBC) with memory
memory into a low-power sleep mode
controller
Both hardware and software options to support
Enhanced secured digital host controller (eSDHC) used for
battery-backed main memory
SD/MMC card interface
Integrated security engine (SEC) optimized to process all
Support boot capability from eSDHC
the algorithms associated with IPsec, IKE, SSL/TLS,
Integrated four-channel DMA controller
2
iSCSI, SRTP, IEEE Std 802.16e, and 3GPP.
Dual I C and dual universal asynchronous
XOR engine for parity checking in RAID storage
receiver/transmitter (DUART) support
applications
Programmable interrupt controller (PIC)
Enhanced Serial peripheral interfaces (eSPI)
Power management, low standby power
Support boot capability from eSPI
Support Doze, Nap, Sleep, Jog, and Deep Sleep mode
Two enhanced three-speed Ethernet controllers (eTSECs)
PMC wake on: LAN activity, USB connection or remote
with SGMII support
wakeup, GPIO, internal timer, or external interrupt event
Three-speed support (10/100/1000 Mbps)
System performance monitor
Two IEEE Std 802.3, IEEE 802.3u, IEEE 802.3x,
IEEE Std 1149.1-compatible, JTAG boundary scan
IEEE 802.3z, IEEE 802.3ac, IEEE 802.3ab, and
783-pin FC-PBGA package, 29 mm 29 mm
IEEE Std 1588-compatible controllers
2011 Freescale Semiconductor, Inc. All rights reserved.Table of Contents
1 Pin Assignments and Reset States . . . . . . . . . . . . . . . . . . . . .3 2.21 PCI Express. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
1.1 Pin Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2.23 Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
2 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 2.24 Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
2.1 Overall DC Electrical Characteristics . . . . . . . . . . . . . .21 3 Hardware Design Considerations . . . . . . . . . . . . . . . . . . . . 114
2.2 Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 3.1 System Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
2.3 Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .26 3.2 Power Supply Design and Sequencing . . . . . . . . . . . 114
2.4 Input Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 3.3 Pin States in Deep Sleep State . . . . . . . . . . . . . . . . . 115
2.5 RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . .31 3.4 Decoupling Recommendations . . . . . . . . . . . . . . . . . 115
2.6 DDR2 and DDR3 SDRAM . . . . . . . . . . . . . . . . . . . . . .32 3.5 SerDes Block Power Supply Decoupling
2.7 eSPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Recommendations. . . . . . . . . . . . . . . . . . . . . . . . . . . 116
2.8 DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 3.6 Connection Recommendations . . . . . . . . . . . . . . . . . 116
2.9 Ethernet: Enhanced Three-Speed Ethernet (eTSEC), 3.7 Pull-Up and Pull-Down Resistor Requirements. . . . . 116
MII Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 3.8 Output Buffer DC Impedance . . . . . . . . . . . . . . . . . . 116
2.10 Ethernet Management Interface Electrical Characteristics 3.9 Configuration Pin Muxing . . . . . . . . . . . . . . . . . . . . . 117
61 3.10 JTAG Configuration Signals . . . . . . . . . . . . . . . . . . . 118
2.11 USB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 3.11 Guidelines for High-Speed Interface Termination . . . 120
2.12 enhanced Local Bus Controller (eLBC) . . . . . . . . . . . .66 4 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
2.13 Enhanced Secure Digital Host Controller (eSDHC) . . .75 4.1 Part Numbers Fully Addressed by this Document. . . 122
2.14 Programmable Interrupt Controller (PIC) . . . . . . . . . . .77 4.2 Part Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
2.15 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 4.3 Part Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
2.16 Serial ATA (SATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 5 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
2
2.17 I C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 5.1 Package Parameters for the FC-PBGA . . . . . . . . . . . 123
2.18 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 5.2 Mechanical Dimensions of the FC-PBGA . . . . . . . . . 124
2.19 PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 6 Product Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
2.20 High-Speed Serial Interfaces . . . . . . . . . . . . . . . . . . . .91 7 Document Revision History. . . . . . . . . . . . . . . . . . . . . . . . . 125
MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
2 Freescale Semiconductor