Document Number: MPC8548EEC Freescale Semiconductor Rev. 10, 06/2014 Technical Data MPC8548E PowerQUICC III Integrated Processor Hardware Specifications Contents 1 Overview 1. Overview . 1 2. Electrical Characteristics . 10 This section provides a high-level overview of the device 3. Power Characteristics 15 features. The following figure shows the major functional 4. Input Clocks . 16 5. RESET Initialization . 19 units within the device. 6. DDR and DDR2 SDRAM . 20 Although this document is written from the perspective of 7. DUART . 26 8. Enhanced Three-Speed Ethernet (eTSEC) 27 the MPC8548E, most of the material applies to the other 9. Ethernet Management Interface Electrical family members, such as MPC8547E, MPC8545E, and Characteristics 41 MPC8543E. When specific differences occur, such as pinout 10. Local Bus . 43 11. Programmable Interrupt Controller . 53 differences and processor frequency ranges, they are 12. JTAG . 53 identified as such. 2 13. I C . 56 14. GPOUT/GPIN 59 For specific PVR and SVR numbers, see the MPC8548E 15. PCI/PCI-X . 60 PowerQUICC III Integrated Host Processor Reference 16. High-Speed Serial Interfaces (HSSI) 65 Manual. 17. PCI Express 73 18. Serial RapidIO . 81 19. Package Description . 91 20. Clocking . 130 21. Thermal 134 22. System Design Information 135 23. Ordering Information . 145 24. Document Revision History 148 Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. 2007-2012, 2014 Freescale Semiconductor, Inc. All rights reserved.Overview Security DDR/DDR2/ DDR Engine SDRAM Memory Controller 512-Kbyte Flash XOR Local Bus Controller SDRAM L2 Cache/ Engine GPIO SRAM e500 Core Programmable Interrupt IRQs Controller (PIC) e500 32-Kbyte L1 32-Kbyte Coherency Core Complex Instruction L1 Data Serial Module DUART Bus Cache Cache 2 I C 2 I C Controller Serial RapidIO 2 I C 2 or 4x RapidIO I C Controller PCI Express x8 PCI Express MII, GMII, TBI, eTSEC OceaN RTBI, RGMII, Switch 10/100/1Gb RMII Fabric PCI 32-bit 32-bit PCI Bus Interface MII, GMII, TBI, eTSEC 66 MHz (If 64-bit not used) RTBI, RGMII, 10/100/1Gb RMII 32-bit PCI/ MII, GMII, TBI, eTSEC PCI/PCI-X 64-bit PCI/PCI-X RTBI, RGMII, 133 MHz Bus Interface 10/100/1Gb RMII eTSEC 4-Channel DMA RTBI, RGMII, Controller RMII 10/100/1Gb Figure 1. Device Block Diagram 1.1 Key Features The following list provides an overview of the device feature set: High-performance 32-bit core built on Power Architecture technology. 32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache with parity protection. Caches can be locked entirely or on a per-line basis, with separate locking for instructions and data. Signal-processing engine (SPE) APU (auxiliary processing unit). Provides an extensive instruction set for vector (64-bit) integer and fractional operations. These instructions use both the upper and lower words of the 64-bit GPRs as they are defined by the SPE APU. Double-precision floating-point APU. Provides an instruction set for double-precision (64-bit) floating-point instructions that use the 64-bit GPRs. 36-bit real addressing Embedded vector and scalar single-precision floating-point APUs. Provide an instruction set for single-precision (32-bit) floating-point instructions. Memory management unit (MMU). Especially designed for embedded applications. Supports 4-Kbyte to 4-Gbyte page sizes. Enhanced hardware and software debug support MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 10 2 Freescale Semiconductor
