Document Number: MPC8569EEC Freescale Semiconductor Rev. 2, 10/2013 Data Sheet: Technical Data MPC8569E MPC8569E PowerQUICC III Integrated Processor Hardware Specifications High-performance, 32-bit e500 core, scaling up to Cryptographic execution units for PKEU, DEU, AESU, 1.33 GHz, that implements the Power Architecture AFEU, MDEU, KEU, CRCU, RNG and SEU- SNOW technology QUICC Engine technology 2799 MIPS at 1.33 GHz (estimated Dhrystone 2.1) Four 32-bit RISC cores 36-bit physical addressing Supports Ethernet, ATM, POS, and T1/E1 along with Double-precision embedded floating point APU using associated interworking 64-bit operands Four Gigabit Ethernet interfaces (up to two with Embedded vector and scalar single-precision SGMII) floating-point APUs using 32- or 64-bit operands Up to eight 10/100-Mbps Ethernet interfaces Memory management unit (MMU) Up to 16 T1/E1 TDM links (512 64 channels) Integrated L1/L2 cache Multi-PHY UTOPIA/POS-PHY L2 interface L1 cache32-Kbyte data and 32-Kbyte instruction (16-bit) L2 cache512-Kbyte (8-way set associative) IEEE Std 1588 v2 support Two DDR2/DDR3 SDRAM memory controllers with full SPI and Ethernet PHY management interface ECC support One full-/low-speed USB interface supporting USB 2.0 One 64-bit or two 32-bit data bus configuration General-purpose I/O signals Up to 400 MHz clock (800 MHz data rate) High-speed interfaces (multiplexed) supporting: Supporting up to 16 Gbytes of main memory Two 1 Serial RapidIO interfaces (with message unit) or Using ECC, detects and corrects all single-bit errors and one 4x interface detects all double-bit errors and all errors within a nibble 4/2/1 PCI Express interface Invoke a level of system power management by Two SGMII interfaces asserting MCKE SDRAM signal on-the-fly to put the On-chip network switch fabric memory into a low-power sleep mode 133 MHz, 16-bit, 3.3 V I/O, enhanced local bus (eLBC) Both hardware and software options to support with memory controller battery-backed main memory Enhanced secured digital host controller (eSDHC) used for Initialization bypass feature that allow system designers SD/MMC card interface to prevent re-initialization of main memory during Integrated four-channel DMA controller system power on following abnormal shutdown 2 Dual I C and dual universal asynchronous Integrated security engine (SEC) optimized to process all receiver/transmitter (DUART) support the algorithms associated with IPsec, IKE, SSL/TLS, Programmable interrupt controller (PIC) iSCSI, SRTP, IEEE Std 802.11i, IEEE Std 802.16 IEEE Std 1149.1 JTAG test access port (WiMAX), IEEE 802.1ae (MACSec), 3GPP, A5/3 for 1.0-V and 1.1-V core voltages with 3.3-V, 2.5-V, 1.8-V, GSM and EDGE, and GEA3 for GPRS. 1.5-V and 1.0-V I/O XOR engine for parity checking in RAID storage 783-pin FC-PBGA package, 29 mm 29 mm applications Four crypto-channels, each supporting multi-command descriptor chains Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. 20112013 Freescale Semiconductor, Inc. All rights reserved.Table of Contents 1 Pin Assignments and Reset States .4 2.17 Timers 110 1.1 Ball Layout Diagrams .4 2.18 Programmable Interrupt Controller (PIC) 111 1.2 Pinout List 9 2.19 SPI Interface . 112 2 Electrical Characteristics 36 2.20 TDM/SI . 114 2.1 Overall DC Electrical Characteristics 36 2.21 USB Interface 116 2.2 Power Characteristics 42 2.22 UTOPIA/POS Interface . 117 2.3 Input Clocks .43 3 Thermal 119 2.4 DDR2 and DDR3 SDRAM Controller 45 3.1 Thermal Characteristics . 119 2.5 DUART .53 3.2 Recommended Thermal Model . 119 2.6 Ethernet Interface .54 3.3 Thermal Management Information 120 2.7 Ethernet Management Interface 74 4 Package Description 121 2.8 HDLC, BISYNC, Transparent, and Synchronous UART 4.1 Package Parameters for the MPC8569E 122 Interfaces .76 4.2 Mechanical Dimensions of the FC-PBGA with Full Lid123 2.9 High-Speed SerDes Interfaces (HSSI) .78 5 Ordering Information 124 2.10 PCI Express .85 5.1 Part Numbers Fully Addressed by This Document 124 2.11 Serial RapidIO (SRIO) .90 5.2 Part Marking . 125 2 2.12 I C .95 5.3 Part Numbering . 125 2.13 GPIO .98 6 Product Documentation 125 2.14 JTAG Controller .99 7 Document Revision History . 126 2.15 Enhanced Local Bus Controller .101 2.16 Enhanced Secure Digital Host Controller (eSDHC) 108 MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 2 2 Freescale Semiconductor