Freescale Semiconductor
Document Number: PXR40
Rev. 1, 09/2011
Data Sheet: Technical Data
PXR40
PXR40 Microcontroller Data
Sheet
TEPBGA416
27mm x 27mm
Dual issue, 32-bit CPU core complex (e200z7) single action, double action, pulse width modulation
Compliant with the Power Architecture embedded (PWM) and modulus counter operation
category Four enhanced queued analog-to-digital converters
16 KB I-Cache and 16 KB D-Cache (eQADC)
Includes an instruction set enhancement allowing Support for 64 analog channels
variable length encoding (VLE), optional encoding of Includes one absolute reference ADC channel
mixed 16-bit and 32-bit instructions, for code size Includes eight decimation filters
footprint reduction Four deserial serial peripheral interface (SPI) modules
Includes signal processing extension (SPE2) instruction Three enhanced serial communication interface (UART)
support for digital signal processing (DSP) and modules
single-precision floating point operations Four controller area network (CAN) modules
4 MB on-chip flash Dual-channel FlexRay controller
Supports read during program and erase operations, and Nexus development interface (NDI) per IEEE-ISTO
multiple blocks allowing EEPROM emulation 5001-2003/5001-2008 standard
256 KB on-chip general-purpose SRAM including 32 KB Device and board test support per Joint Test Action Group
of standby RAM (JTAG) (IEEE 1149.1)
Two direct memory access controller (eDMA2) blocks On-chip voltage regulator controller regulates supply
One supporting 64 channels voltage down to 1.2 V for core logic
One supporting 32 channels
Interrupt controller (INTC)
Frequency modulated phase-locked loop (FMPLL)
Crossbar switch architecture for concurrent access to
peripherals, flash, or RAM from multiple bus masters
External bus interface (EBI) for calibration and application
development (not available on all packages)
System integration unit (SIU)
Error correction status module (ECSM)
Boot assist module (BAM) supports serial bootload via
CAN or SCI
Two second-generation enhanced time processor units
(eTPU2) that share code and data RAM.
32 standard channels per eTPU2
24 KB code RAM
6 KB parameter (data) RAM
Enhanced modular input output system supporting 32
unified channels (eMIOS) with each channel capable of
Freescale Semiconductor, Inc., 2011. All rights reserved.Table of Contents
1 PXR40 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 5.9 eQADC electrical characteristics. . . . . . . . . . . . . . . . . 68
2 PXR40 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 5.9.1 ADC internal resource measurements. . . . . . . 69
3 Pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 5.10 C90 flash memory electrical characteristics . . . . . . . . 71
3.1 416-ball TEPBGA pin assignments. . . . . . . . . . . . . . . . .6 5.11 AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
4 Signal properties and muxing . . . . . . . . . . . . . . . . . . . . . . . . .11 5.11.1 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 5.11.2 Pad AC specifications. . . . . . . . . . . . . . . . . . . . 74
5.1 Maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 5.12 AC timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
5.2 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . .53 5.12.1 Generic timing diagrams . . . . . . . . . . . . . . . . . 77
5.2.1 General notes for specifications at maximum junction 5.12.2 Reset and configuration pin timing. . . . . . . . . . 78
temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 5.12.3 IEEE 1149.1 interface timing . . . . . . . . . . . . . . 78
5.3 EMI (Electromagnetic Interference) characteristics . . .55 5.12.4 Nexus timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 81
5.4 ESD characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . .56 5.12.5 External Bus Interface (EBI) timing . . . . . . . . . 84
5.5 PMC/POR/LVI electrical specifications . . . . . . . . . . . . .56 5.12.6 External interrupt timing (IRQ pin) . . . . . . . . . . 88
5.6 Power up/down sequencing . . . . . . . . . . . . . . . . . . . . .59 5.12.7 eTPU timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
5.6.1 Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 5.12.8 eMIOS timing . . . . . . . . . . . . . . . . . . . . . . . . . . 89
5.6.2 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 5.12.9 DSPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
5.6.3 Power sequencing and POR dependent on V 60 6 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
DDA
5.7 DC electrical specifications . . . . . . . . . . . . . . . . . . . . . .61 6.1 Orderable parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
5.7.1 I/O pad current specifications . . . . . . . . . . . . . .64 7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
5.7.2 I/O pad V current specifications . . . . . . . . .64 7.1 416-pin package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
DD33
5.7.3 LVDS pad specifications . . . . . . . . . . . . . . . . . .65 8 Product documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
5.8 Oscillator and FMPLL electrical characteristics . . . . . .66 9 Revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
PXR40 Microcontroller Data Sheet, Rev. 1
2 Freescale Semiconductor