Freescale Semiconductor Document Number: PXS20 Rev. 1, 09/2011 Data Sheet: Advance Information PXS20 MAPBGA225 QFN12 15 mm x 15 mm mm x mm SOT-343R PKG-TBD PXS20 Microcontroller Data mm x mm mm x mm TBD 144 LQFP 257 MAPBGA Sheet (20 x 20 x 1.4 mm) (14 x 14 x 0.8 mm) GPIOs individually programmable as input, output or High-performance e200z4d dual core special function 32-bit Power Architecture technology CPU Three 6-channel general-purpose eTimer units Core frequency as high as 120 MHz 2 FlexPWM units Dual issue five-stage pipeline core Four 16-bit channels per module Variable Length Encoding (VLE) Communications interfaces Memory Management Unit (MMU) 2 LINFlexD channels 4 KB instruction cache with error detection code 3 DSPI channels with automatic chip select generation Signal processing engine (SPE) 2 FlexCAN interfaces (2.0B Active) with 32 message Memory available objects 1 MB flash memory with ECC FlexRay module (V2.1 Rev. A) with 2 channels, 64 128 KB on-chip SRAM with ECC message buffers and data rates up to 10 Mbit/s Built-in RWW capabilities for EEPROM emulation Two 12-bit analog-to-digital converters (ADCs) SIL3/ASILD innovative safety concept: LockStep mode 16 input channels and Fail-safe protection Programmable cross triggering unit (CTU) to Sphere of replication (SoR) for key components (such as synchronize ADCs conversion with timer and PWM CPU core, eDMA, crossbar switch) Sine wave generator (D/A with low pass filter) Fault collection and control unit (FCCU) On-chip CAN/UART bootstrap loader Redundancy control and checker unit (RCCU) on Single 3.0 V to 3.6 V voltage supply outputs of the SoR connected to FCCU Ambient temperature range 40 C to 125 C Boot-time Built-In Self-Test for Memory (MBIST) and Junction temperature range 40 C to 150 C Logic (LBIST) triggered by hardware Boot-time Built-In Self-Test for ADC and flash memory triggered by software Replicated safety enhanced watchdog Replicated junction temperature sensor Non-maskable interrupt (NMI) 16-region memory protection unit (MPU) Clock monitoring units (CMU) Power management unit (PMU) Cyclic redundancy check (CRC) unit Decoupled Parallel mode for high-performance use of replicated cores Nexus Class 3+ interface Interrupts Replicated 16-priority controller Replicated 16-channel eDMA controller This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. Freescale Semiconductor, Inc., 2011. All rights reserved. PreliminarySubject to Change Without NoticeTable of Contents 1 Introduction 3 1.5.40 IEEE 1149.1 JTAG Controller (JTAGC) 21 1.1 Document overview .3 1.5.41 Nexus Port Controller (NPC) 22 1.2 Description .3 2 Package pinouts and signal descriptions . 23 1.3 Device comparison .3 2.1 Package pinouts . 23 1.4 Block diagram .6 2.2 Supply pins . 52 1.5 Feature details 7 2.3 System pins . 54 1.5.1 High-Performance e200z4d Core 7 2.4 Pin muxing 54 1.5.2 Crossbar Switch (XBAR) .8 3 Electrical characteristics 73 1.5.3 Memory Protection Unit (MPU) 8 3.1 Introduction . 73 1.5.4 Enhanced Direct Memory Access (eDMA) .9 3.2 Absolute maximum ratings . 73 1.5.5 On-Chip Flash Memory with ECC 9 3.3 Recommended operating conditions 74 1.5.6 On-Chip SRAM with ECC 9 3.4 Thermal characteristics 75 1.5.7 Platform Flash Memory Controller .10 3.4.1 General notes for specifications at maximum 1.5.8 Platform Static RAM Controller (SRAMC) .10 junction temperature . 76 1.5.9 Memory Subsystem Access Time .11 3.5 Electromagnetic Interference (EMI) characteristics (cut1) 77 1.5.10 Error Correction Status Module (ECSM) 11 3.6 Electrostatic discharge (ESD) characteristics . 78 1.5.11 Peripheral Bridge (PBRIDGE) 11 3.7 Static latch-up (LU) . 79 1.5.12 Interrupt Controller (INTC) .11 3.8 Voltage regulator electrical characteristics . 79 1.5.13 System Clocks and Clock Generation 12 3.9 DC electrical characteristics 82 1.5.14 Frequency-Modulated Phase-Locked Loop 3.10 Supply current characteristics (cut2) 83 (FMPLL) .12 3.11 Temperature sensor electrical characteristics . 84 1.5.15 Main Oscillator 13 3.12 Main oscillator electrical characteristics . 84 1.5.16 Internal Reference Clock (RC) Oscillator 13 3.13 FMPLL electrical characteristics . 86 1.5.17 Clock, Reset, Power Mode, and Test Control 3.14 16 MHz RC oscillator electrical characteristics 88 Modules (MC CGM, MC RGM, MC PCU, and 3.15 ADC electrical characteristics . 88 MC ME) 13 3.15.1 Input Impedance and ADC Accuracy 88 1.5.18 Periodic Interrupt Timer Module (PIT) 13 3.16 Flash memory electrical characteristics . 93 1.5.19 System Timer Module (STM) .14 3.17 SWG electrical characteristics . 94 1.5.20 Software Watchdog Timer (SWT) .14 3.18 AC specifications . 94 1.5.21 Fault Collection and Control Unit (FCCU) .14 3.18.1 Pad AC specifications 94 1.5.22 System Integration Unit Lite (SIUL) 14 3.19 Reset sequence 95 1.5.23 Non-Maskable Interrupt (NMI) 15 3.19.1 Reset sequence duration . 96 1.5.24 Boot Assist Module (BAM) .15 3.19.2 Reset sequence description . 96 1.5.25 System Status and Configuration Module (SSCM) 15 3.19.3 Reset sequence trigger mapping . 98 1.5.26 Controller Area Network Module (CAN) 15 3.19.4 Reset sequence start condition . 100 1.5.27 FlexRay .16 3.19.5 External watchdog window . 101 1.5.28 Serial Communication Interface Module (UART)16 3.20 AC timing characteristics 101 1.5.29 Serial Peripheral Interface (SPI) 17 3.20.1 RESET pin characteristics . 102 1.5.30 Pulse Width Modulator (PWM) .17 3.20.2 WKUP/NMI timing . 103 1.5.31 eTimer Module 18 3.20.3 IEEE 1149.1 JTAG interface timing 103 1.5.32 Sine Wave Generator (SWG) 19 3.20.4 Nexus timing 105 1.5.33 Analog-to-Digital Converter Module (ADC) 19 3.20.5 External interrupt timing (IRQ pin) . 107 1.5.34 Junction Temperature Sensor 20 3.20.6 DSPI timing 108 1.5.35 Cross Triggering Unit (CTU) .20 4 Package characteristics 113 1.5.36 Cyclic Redundancy Checker (CRC) Unit 20 4.1 Package mechanical data . 113 1.5.37 Redundancy Control and Checker Unit (RCCU)21 5 Ordering information 118 1.5.38 Voltage Regulator / Power Management Unit (PMU)21 6 Document revision history 118 1.5.39 Built-In Self-Test (BIST) Capability 21 PXS20 Microcontroller Data Sheet, Rev. 1 2 Freescale Semiconductor PreliminarySubject to Change Without Notice